Prof. Qureshi

Name: Shafi Qureshi
Date of Birth: June 10, 1953
Present position: Professor (13 years)
Department of Electrical Engineering,
I. I. T. Kanpur
Kanpur-208016
India
E-mail: qureshi@iitk.ac.in
Phone: +91-512-2597133
Fax: +91-512-2590063
B. E. (University of Kashmir, India, year 1974)

Ph. D (University of California, Berkeley, USA, Year 1991)
M. S. (University of California, Berkeley, USA, Year 1986)
Graduation (Atomic Energy Training School, Trombay, Bombay, India, Year 1976)
B. E. (University of Kashmir, India, year 1974)

Courses Taught at I.I.T. Kanpur
EE 614: Electron Devices and Circuits (post-graduate)
EE 311: Electron devices and Circuits (undergraduate)
ESc 202: Electronics: Analog and Digital (undergraduate)
ESc 101: Introduction to Electronics
EE 611: Analog VLSI Circuit Design (post-graduate/undergraduate)
EE 619: Digital System Design (post-graduate/undergraduate)
EE 381: Electronic Circuits Lab. (undergraduate)
NT 621: Nuclear Measurement Techniques (Postgraduate)

Courses Taught at University of Malaysia, Sarawak during one year sabbatical (December 2002- December 2003)<br/> KNL 2153: Electron Devices and Circuits (undergraduate)
KNL 2383: Electronic Circuits
KNL 4213: VLSI Design and Technology
Administered VLSI Design Laboratory at University of Malaysia, Sarawak, Malaysia

Semiconductor Device Physics and Modeling
VLSI Circuit Design
RFID Tag Chip Design

1992 onwards: Teaching and Research at I.I.T. Kanpur
1986-1991: Research Associate Lawrence Berkeley Laboratory, USA
1981-1984: Electrical Engineer, Yanbu, Saudi Arabia
1976-1981: Department of Atomic Energy, India

Senior Member IEEE
Fellow IETE
Life Member IARP

1. "Remote Service Machine RSM” Patent Application No. 932/DEL/2008, Dated: 09-04-2008, Inventors : S. Qureshi,, Mayank Raj & Gopesh Mittal
2. “An Improved Lateral Bipolar Junction (BJT) on selective buried oxide (SELBOX) and a method for manufacturing the same”, Patent Application No. 1478/DEL/2008, Dated: 20-06-2008, Inventors name: Qureshi S., Iyer S. S. K. & Lone S. A.

• Coordinator, Academic Senate year 2007-8
• Member SSAC year 2009-10
• Chairman, SUGC year 1998-99
• Warden, Girl’s Hostel 2002

Developed State-of-the-Art VLSI / EDA Design Laboratory equipped with Industry Standard Digital and Analog Design Tools at I.I.T. Kanpur

(i) Digital Circuit Design
(ii) Synthesis of Digital systems
(iii) Low Power VLSI Design

(i) Coordinator of Project on Special Manpower Development Program in VLSI Design and Related Software (SMDP-II) Sponsored by Ministry of Communication and Information Technology, India, year 2005 -2010
(ii) Coordinator National RFID Programme, year 2009 onwards
(iii) Establishing CAD facilities for Mixed Signal and MEMS Design, year 2005-2006

(a) Activity at National Level
Responsible for Design and Tape out of first application specific integrated circuit (ASIC) at I. I. T. Kanpur. The tape out has been sent for fabrication to Euro-practice in Belgium. Chip has designs from three N. I .T.s also.
(ii) To raise share of India in VLSI Design activity in the world market I have been promoting VLSI Design activity in the country by offering courses to N.I.T teachers, and N.I.T and I.I.I.T students. I have offered summer training to students of public and private colleges numbering over forty students in the last three years in the area of VLSI Design. Further, designs from three institutes (N.I.T) and government organization (D.I.T.) have been integrated at I.I.T Kanpur on a chip and sent for fabrication.
(b) Activity at International Level
I was Coordinator of ten member Indian delegation visiting National Tsing Hua University, Taiwan, to promote Research Collaboration between India and Taiwan in the area of VLSI Design. The visit took place in November 2 – 3, 2009. The workshop conducted in Taiwan during the visit was jointly funded by DST and its counterpart agency NSC from Taiwan.

Number of Ph. D students Guided or Currently Under Guidance
Five
1. Completed
M. J. Siddqui
Thesis Title: “Models for DC Characteristics of Poly-silicon Thin Film transistors”
2. Submitted
Sajad A. Loan
Thesis title: “Simulation of SELBOX MOSFET and Lateral Bipolar Junction transistor (LBJT) on SOI with Selective or Modified Buried Oxide Structures”.
3. S. Choudhary
4. P. Ganesh
5. P. K. Misra
Citation to Research Paper
A paper by Siddiqui M. J. & Qureshi S., titled “Surface-Potential-Based Charge Sheet Model for the Polysilicon Thin Film Transistors Without Considering the Kink Effect”, Microelectronics Journal, 32 (2001) 235-240 is being cited repeatedly.

1. Loan S. A., Qureshi S. & Kumar Iyer S. S., “ A Novel Partial-Ground-Plane-Based MOSFET on Selective Buried Oxide: 2-D Simulation Study” IEEE Trans. Electron Devices, Vol. 57, No. 3 (2010), 671-680
2. Loan S. A., Qureshi S. & Kumar Iyer S. S., “A Novel High Breakdown Voltage Lateral Bipolar Transistor on SOI with Multi-zone Doping and Multi-step Oxide”, Semiconductor Science and Tech., Vol. 24, No. 2, (2009)
3. Choudhary S. & Qureshi S. “Power Aware Channel Width Tapering of Serially Connected MOSFETs”, Australian Journal of Electrical and Electronics Engineering, Vol. 5, No. 1, (2008), 35-42
4. Choudhary S. & Qureshi S. “Input Noise Modeling of Deep Submicron MOSFETs”, Australian Journal of Electrical and Electronics Engineering, Vol. 4, No. 3, 2008, 1-6
5. Qureshi S. & Siddiqui M. J., “A DC Charge Sheet Model for the I-V Characteristics of Doped Polysilicon Thin Film Transistor”, Semiconductor Science and Technology, No. 17 (2002) , 526-533.
6. Siddiqui M. J. & Qureshi S. ,”Surface-Potential-Based Charge Sheet Model for the Polysilicon Thin Film Transistors Without Considering the Kink Effect”, Microelectronics Journal, 32 (2001) 235-240
7. Siddiqui M. J. & Qureshi S., “An Empirical Model for Leakage Current in Polysilicon Thin Film Transistor”, Solid State Electronics, 44 (2000) 2015-2019
8. Cho G., Qureshi S., Drewery J. S., Jing T., Kaplan S. N., Lee H, Mireshghi A., Perez-Mendez V., & Wildermuth D.,”Noise in a-Si:H p-i-n Diodes” IEEE Trans. Nucl. Sci. Vol. 39, No.4, (1992), 641-644
9. Perez-Mendez V., Cho G., Drewery J., Jing T., Kaplan S. N., Qureshi S., Wildermuth D., Fujieda I. , & Street R. A.”Amorphous Silicon Based Radiation Detectors”, Journal of Non- Crystalline Solids, 137 & 138 (1991) 1291-1296
10. Cho G., Conti M., Drewery J. S., Fujieda I. , Kaplan S. N., Perez-Mendez V., Qureshi S. and Street R. A., “Assessment of TFT Amplifier for a-Si:H Pixel Particle Detector”, IEEE Trans. Nucl. Sci, NS-37, (1990), 1142
11. Cho G., Drewery J., Fujieda I, Kaplan S. N., Qureshi S., Perez-Mendez V. & Street R. A, “Measurement of 1/f Noise in a-Si:H PIN Diodes and Thin Film Transistors”, IEEE Trans. Nucl. Sci. S_37 (1990)
12. Qureshi S., Perez-Mendez V., Kaplan S. N., Fujieda I. Cho. G., & Street R. A., “Signal Generation in Hydrogenated Amorphous Silicon Detectors”, IEEE Trans. Nucl. Sci, Vol. 36, No. 1, (1989), 194-198
13. Qureshi S., Cho G., Fujieda I, Kaplan S. N., Perez-Mendez & Street R. A., “Material Para- meters in Thick a-Si:H Radiation Detectors”, J. Non-Crystalline Solids”, Vol. 114 (1989), 417-419
14. Fujieda I., Cho G., Kaplan S. N., Perez-Mendez V., Qureshi S. & Street R. A. “Applications of a-Si:H Radiation Detectors”, J. Non-crystalline Solids 115 (1989) 174-176
15. Perez-Mendez V, Kaplan S. N., Ward W., Qureshi S. and Street R A., “Signal recombination Effects and Noise in a-Si:H Detectors”, Nucl. Instr. Meth. A 260 (1987) 195
16. Perez-Mendez V., Kaplan S. N., Cho G., Fujieda I, Qureshi S., Ward W. and Street R. A. “Hydrogenated Amorphous Silicon Pixel Detectors for Minimum Ionizing particles”, Nucl. Instr. Meth. A273 (1988) 127
17. Kaplan S. N., Fujieda I., Perez-Mendez V., Qureshi S., Ward W. & Street R. A., “Detection of Minimum Ionizing Particles In Hydrogenated Amorphous Silicon”, Nucl. Instr. Meth. A273, (1988) 611
18. Qureshi S. & Vijendaran P., “Pump Down Equation and Its Practical Implication”, Vac News, Vol. 10, 7-13, No. 1, (1979),

1. Qureshi S. Loan S. A.& Iyer S. S. K., “A High Performance MOSFET on Selective Buried Oxide”, ISDRS December 2009, University of Maryland, USA
2. Loan S. A., Qureshi S. & Iyer S. S. K., “A High Performance Lateral Bipolar Junction Transistor on Selective Buried Oxide”, ISDRS December 2009, University of Maryland, USA.
3. Qureshi S. & Sanjeev K. R., “Power and Performance Optimization using Mult-voltage, Multi-threshold and Clock Gating for Low End Micro-processors”, IEEE TENCON Conference, October 2009, Singapore, 1-6
4. Loan S. A., Qureshi S. & Iyer S. S. K., “Investigation of a New Partial Ground Plane Based MOSFET on Selective Buried Oxide”, Spanish Conference on Electron Devices, CDE, Feb. 2009.
5. Loan S. A., Qureshi S. & Iyer S. S. K., “A Numerical Simulation of a Nanoscaled Side Selective Buried Oxide MOSFET”, IEEE Electron Devices and Solid State Circuits Conference EDSSC, Hong Kong, December 2008
6. Loan S. A., Qureshi S. & Iyer S. S. K., “A Novel Multi-zone Doped and Multi-step Oxide High Breakdown Voltage Lateral Bipolar Transistor on SOI”, IEEE ICSE Conference, Malysia, November 2008
7. Lone S. A., Qureshi S. & Iyer S. S. K., “High Breakdown Voltage Two Zone Step Doped Lateral Bipolar Transistor on Burried Oxide”, World Congress on Engineering 2008, London, July 2-4
8. Choudhary, S.; Qureshi, S.; “Life Time Issues in Organic Light Emitting Diodes”, IEEE TENCON Conference, November 2008
9. Choudhary S. & Qureshi S., “Power Aware Channel Tapering of Serially Connected MOSFETs”, IEEE International Conference on Microelectronics, (IEEE-ICM07), Cairo, Egypt, December 29 - 31, 2007, 412-415, ISBN: 978-1-4244-1847-3
10. Choudhary, S & Qureshi, S, “Input Noise Modeling of Deep Submicron MOSFETs”, IEEE International Microwave & Optoelectronics Conference, (IMOC 2007), Brazil October 29- November 1, 2007, 175-179, ISBN: 978-1-4244-0661-6
11. Qureshi, S. & Chhabra, G. “One-Dimensional Sub-Threshold Model for Symmetric Double-Gate MOSFETs” , International Semiconductor Device Research Symposium (ISDRD-2005), December 7- December 9, Bethesda, Maryland, U.S.A.
12. Qureshi, S. & Suaidi M. K.., “Enhancing Chip Design Activity in Malaysia-Role of Malaysian Universities”, Engineering and Technology (ENTECH 2003) Conference, July 31-Aug 2, Kuching, Sarawak, Malaysia.
13. Qureshi, S., Perez-Mendez V. Kaplan S. N., Fujieda I., Cho G. & Street R. A., “Material Parameters in Thick Hydrogenated Amorphous Silicon Detector Diodes and Their Effects on Signal Collection” Mat. Res. Soc. Symp. Proc. Vol. 149, 1989, 649-654
14. Perez-Mendez V., Cho G., Fujieda I., Kaplan S. N., Qureshi S., & Street R. A.,”Application of Thick Hydrogenated Amorphous Silicon layers to Charged Particles and X-ray Detection”, Proc. Mat. Res. Soc. Vol. 149 1989, 621
15. Qureshi S., Ward W., Kaplan S. N., Perez-Mendez V., “Radiation Damage in Amorphous Silicon particle Detectors”, Bull. Am. Phys. Soc. 32, No. 1, 1987, 66
16. Perez-Mendez V., Cho G, Drewery D., Fujieda I., Kaplan S. N., Qureshi S. & Street R. A. “Properties of Hydrogenated Amorphous Silicon Detectors In charged Particles, gamma Ray and light Detection”, LBL Report ? 28339, Feb. 1990
17. Siddiqui M. J. & Qureshi S., “An Explicit Surface Potential Formulation for Doped Polysilicon Thin Film Transistor”, Proc. 24th National Systems Conference Bangalore,India, 2000, 513-519
18. Qureshi S., “Hydrogenated Amorphous Silicon Pixel Arrays for Imaging and Radiation Detection Applications- An overview”, Proc. Symp.On Advances in Instrumentation, (1997), Sanai-97 , Bombay