Aasif
"chips don't lie- if you are sloppy, your silicon will not work"...Shanthi Pavan
About Me:
I am a Graduate student, working with Dr. Imon Mondal in Department of Electrical Engineering, IIT Kanpur .
I am presently working on the design of a Linear periodically time-varying (LPTV) N-path based low-loss, all-passive, compact wideband true-time-delay Line for sub-6GHz applications using TSMC 65nm technology node. The design was taped-out to TSMC in September 2023 .
Previously, I have designed low power, compact active true-time delay element based 4-channel Beamformer Integrated circuit for sub 6-GHz applications. The project was taped-out to TSMC in Feb 2022.
Research Interests:
Delay Lines, BeamFormers, mm-wave Power amplifiers
Lab: Western Labs (WL)-211, EE, IIT Kanpur,UP, India 208016