Broad Areas:
  • Delay Lines
  • mm-wave circuits
  • Power Amplifiers
  • Beamformers
  • Designed Sub-block/Circuits:
  • LNA, Fully DIfferential OTAs, Tracking Loops(Gm track, Negative resistance Tracking).
  • SAR DAC, Calibration Loops, Output Drivers, Comparator circuitry.
  • Single ended and fully differential OpAmps, CMFB Loops, Digital Delay blocks.
  • 8-phase (12.5% Duty cycle) Clock generator, Pulse Generator Module.
  • Calibration and SPI modules:Verilog to gds involving simulation to signoff(Incisive, Genus, Innovus, Cadence gds import).
  • Conference:
  • Mohmad Aasif Bhat and Ab Mateen Tantray, "CMOS LNA linearization techniques: A comparative analysis," Proceedings of 5th International Conference on Nanotechnology for Better Living (NBL-2019), IIT-Kgp, April 2019.
  • Mohmad Aasif Bhat and Imon Mondal, "A Low-Loss, Compact Wideband True-Time-Delay Line for Sub-6GHz Applications using N-Path Filters," To apear in 2023 Asia Pacific Conference on Circuits and Systems (IEEE APCCAS).
  • A Beamformer for ultra wideband (1-6GHz) Applications
    I have been involved in the design of A Compact Beamforming Receiver for Wideband Imaging in 65nm CMOS Process.
    Beamforming is a technique used to achieve directional communication and reconfigurability in the beam-patterns of an Antenna. The core of this technique is electronically controlled variable delay element.
    The primary focus of this work is on the efficient realization of truetime delay elements with improved performance in terms of delay-range and resolution, bandwidth, power, area and eventually a compact wideband beamforming receiver.
    The project was implemented in TSMC 65nm CMOS process and taped-out for fabrication at TSMC,Taiwan in Feb 2022.
    An all-passive, compact low-loss delay line for wideband beamforming applications
    We have explored Linear periodically time-varying (LPTV) N-path circuits to achieve delay architecture with wider instantaneous bandwidth (3GHz). The proposed architecture substantially reduces the chip area and insertion loss, while achieving a DBW product of 4, outperforming the state-of-the-art DL architectures.
    The project was implemented in TSMC 65nm CMOS process and taped-out for fabrication to TSMC,Taiwan in September 2023.
    Lab: Western Labs (WL)-211, EE, IIT Kanpur,UP, India 208016