Teaching

EE698G: Circuit Design for Frequency & Phase Synthesis

Course Description

This course is all about clock and delay generation circuits. We are going to learn how to analyze a clock signal, how to generate delays and oscillations, how to use feedback (both positive and negative) to our advantage in these circuits and much more.

Course Syllabus

This course will cover the following topics.

• Delay lines

• Delay-locked loops

• Small signal phase domain models

• Phase noise, jitter

• Oscillators

• Phase-locked loops

References

No particular course reference. Please follow the lectures carefully and do the assignments diligently. The course content has been developed based on multiple resources, including

• Behzad Razavi, “Design of CMOS phase-locked loop: From circuit level to architectural level”

• Video lectures on phase-locked loops by Dr. Saurabh Saxena, IIT Madras

• Behzad Razavi, “Design of analog CMOS integrated circuits"