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Yogesh S. Chauhan
'Class of 1984' Chair Professor Fellow IEEE WL125, Department of Electrical Engineering Indian Institute of Technology Kanpur Kanpur, U.P. - 208016, India
Contact: Email: chauhan@iitk.ac.in Internal Phone: 7244 Phone No.: +91-512-6797257 (landline), +91-9044288324 (mobile), Fax: +91-512-2590063
Lab: NanoLab (WL-215)
- Our industry standard ASM-HEMT Model is now available in EDA tools - AWR Microwave Office, AMCAD-IVCAD, Keysight, Parameter Extraction Video, Silvaco-SmartSpice, Harmony, Utmost-IV.
- We have signed NDA to collaborate on new technology development with ST Microelectronics, Micron, Qualcomm, Intel, TagoreTech, Maxlinear, Applied Materials, AMCAD, Global Foundries.
- EE698F (RF Microelectronics)
- EE681 (Compact Modeling)
- EE616 (Semiconductor Device Modeling)
- EE614 (Solid State Devices - I)
- EE370 (Digital Electronics and Microprocessor Technology)
- EE210 (Microelectronics - I)
- ESC201A (Introduction to Electronics)
- EE381A-EC Labortory
- Chair of IEEE EDS Compact Modeling committee (2021-2022)
- Chairperson - IEEE Electron Devices Society, U.P. chapter, Kanpur (2021-2022)
- Vice-Chairman of IEEE U.P. section (2018-2019)
- Convener, Department Postgraduate Committee, IIT Kanpur (2017-2018)
- Convener of Award and recognition committee of IEEE U.P. section (2017)
- Founding Chairperson - IEEE Electron Devices Society, U.P. chapter, Kanpur (2016-2018)
- Warden in-charge (2015-2016) and Warden (2014-2015) of Hall 10, IIT Kanpur
- Executive committee member of IEEE U.P. section (2013-2015, 2017)
- Member, DPGC committee IIT Kanpur (2012-2017)
| Year | Organisation | Designation | Responsibilities |
|---|---|---|---|
| 2019- | IIT Kanpur | Professor | Teaching and Research |
| 2015-2019 | IIT Kanpur | Associate Professor | Teaching and Research |
| 2012-2015 | IIT Kanpur | Assistant Professor | Teaching and Research |
| 2010-2012 | University of California Berkeley | Postdoctoral fellow and BSIM Program Manager | BSIM Model development & support DC, CV and RF Characterization |
| 2010 | Tokyo Institute of Technology, Tokyo, Japan | Postdoctoral Fellow | Modelling and Simulation of MEMS |
| 2007-2010 | IBM Bangalore | Manager/Advisory Research Engineer | Compact Model Extraction, Testsite Design |
| 2003-2004 | ST Microelectronics | Associate Design Engineer | VLSI I/O Library |
