R.S. Ashwin Kumar
Assistant Professor,
Dept. of Electrical Engg.,
IIT Kanpur.
Solid-state circuit design lab
Office: WL 120
Tel: +91-512-259-2165
email: ashwinrs@iitk.ac.in
I work in the area of analog & mixed-signal integrated circuits and signal processing. My current focus is to design power-efficient analog-to-digital converters (ADCs) for biosensors and wireless receivers.
Research with me!
The research work with me usually takes the following flow. After the inception and a top-level verification of an idea, we design the circuit and send it for fabrication. We then design a printed circuit board (PCB) for testing and characterizing the fabricated chip and corroborate the proposed idea with the measured results from the chip! And such a successful chip usually finds its way to a good journal or a conference!
If you are interested to work with me, mail me your CV/resume.
Published works
A discrete-time delta-sigma modulator with relaxed driving & improved anti-aliasing (ISCAS'21)
In this work, a switched-capacitor integrator is proposed for discrete-time delta-sigma modulators (DTDSMs). The proposed integrator samples the signal in an interleaved fashion during the two non-overlapping clocks that are already available in a DTDSM. This not only reduces the effective sampling capacitance in each phase but also introduces notches in the signal transfer function at odd multiples of the sampling frequency. This in turn relaxes the anti-alias filter requirements.
My prior work had focused on realizing multi-channel delta-sigma ADC.
Background
Many sensor applications require precise digitization of multiple analog signals. This requires a high-resolution multi-channel analog-to-digital converter (ADC). A multi-channel ADC is typically realized by sequentially feeding the inputs from multiple channels (multiplexing) to a single ADC and then de-serializing the ADC output. Delta-sigma ADCs are the usual choice for realizing a high-resolution ADC. A DS-ADC relies on filtering (long-term averaging) the noise to reduce its effect within the signal bandwidth of interest. As a result of this filtering, the ADC has a long memory of its past inputs. As a result, when inputs from multiple channels are fed sequentially, the outputs after de-serializing will have severe cross-talk. The conventional solution to prevent cross-talk in a DS-ADC is to reset the ADC before switching to a new input. Such a periodically reset DS-ADC is called the incremental DS-ADC. Resetting the ADC erases the memory of the other inputs, thereby preventing cross-talk. However, this reset compromises the long-term averaging, thereby reducing the signal-to-noise ratio.
The following are some of the techniques I proposed to prevent or cancel cross-talk without resetting the DS-ADC.
Memoryless multi-channel delta-sigma ADC using an additional sample-and-hold & an inverse filter as an equalizer (TCAS1'2018)
In this work, a switched-capacitor integrator is proposed for discrete-time delta-sigma modulators (DTDSMs). The proposed integrator samples the signal in an interleaved fashion during the two non-overlapping clocks that are already available in a DTDSM. This not only reduces the effective sampling capacitance in each phase but also introduces notches in the signal transfer function at odd multiples of the sampling frequency. This in turn relaxes the anti-alias filter requirements.
Cascade of frequency-shifted filters ("pi-shifted filter" for two-channels): New class of filters to avoid cross-talk in multi-channel environments (TCAS1'2020)
This work analyzed the issue of cross-talk in a multi-channel in detail. It is shown that using an inverse filter as an equalizer is a sufficient but not necessary condition to prevent cross-talk. The necessary condition on the filter's transfer function is derived to avoid cross-talk. And this new filter requires a much lower order (and hence consumes a lower power) than the inverse filter.
A two-channel continuous-time delta-sigma ADC is designed and used as the test vehicle to demonstrate this technique. The proposed "pi-shifted filter" reduced the overall power consumption by 35%. The measured signal-to-noise ratio (SNR) is 90.5dB in a 24kHz bandwidth, while the cross-talk was better than -80dBc with the pi-shifted filter, while it was -78dBc with the inverse filter.
Cross-talk free delta-sigma ADC without the additional sample-and-hold by using a modulated-sinc-sum filter (ESSCIRC'2019 & TCAS1'2021)
This work, for the first time, presented a new technique to use a reset-free delta-sigma ADC as a multi-channel ADC only by using a digital filter at the output. This eliminates the need for the additional sample-and-hold required in my earlier works. This solution is at least 36% more power-efficient than a conventional incremental delta-sigma ADC (i.e., a periodically reset DS-ADC).
A two-channel discrete-time DS-ADC was designed and fabricated along with the digital filters in a 180nm CMOS process to verify the proposed technique. The measured SNR is 94.4dB in a 24kHz bandwidth, and this work achieves an excellent cross-talk of -93dBc across temperature (without any additional calibration) and the entire bandwidth.