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Submitted Work:

Currently, there are no active Preprints that have not been submitted.

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Journal Publications:

1. Arka Chakraborty, Musaib Rafiq, Yawar Hayat Zarkob, Yogesh Singh Chauhan, and Shubham Sahay, "Ferroelectric FET based Bayesian Inference Engine for Disease Diagnosis", IEEE Transactions on Circuits and Systems - I, 2025

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2. Yawar Hayat Zarkob, Dinesh Rajasekharan, Ahtisham Pampori, Ayushi Sharma, Girish Pahwa, Debashish Nandi, Chetan Kumar Dabhi, Volker Kubrak, Bob Peddenpohl, Mingchun Tang, Chenming Hu, and Yogesh Singh Chauhan, "Impact Ionization in LDMOS Transistors: Improved Compact Model and Asymmetry under Forward and Reverse Modes of Operation", IEEE Journal of the Electron Devices Society, 2025

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3. Ayushi Sharma, Yawar Hayat Zarkob, Girish Pahwa, Chetan K. Dabhi, Ravi Goel, Harshit Agarwal, Volker Kubrak, Mingchun Tang, Maximilian Treiber, Chenming Hu, and Yogesh Singh Chauhan, "Compact Modeling of Impact Ionization and Conductivity Modulation in LDMOS Transistors", IEEE Transactions on Electron Devices, 2024.

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Conference Publications:

1. Yawar Hayat Zarkob, Dinesh Rajasekharan, Ahtisham Pampori, Ayushi Sharma, Sayeef Salahuddin, Chenming Hu, and Yogesh Singh Chauhan, "Recent Enhancements in the Industry Standard BSIM-BULK Compact Model", International Compact Modeling Conference (ICMC), CA, USA, 2025.

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2. Yawar Hayat Zarkob, Mohammad Sajid Nazir, Ateeb Naseer, Ahtisham Pampori, Chetan Kumar Dabhi, Dinesh Rajasekharan, Zhu Chaosong, Leang Sern Ee, Chenming Hu, and Yogesh Singh Chauhan, "Characterization and Modeling of Flicker Noise in Bulk MOSFETs down to Sub-Threshold Regime", International Compact Modeling Conference (ICMC), CA, USA, 2025.

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3. Wajid Manzoor, Nisha Manzoor, Yawar Hayat Zarkob, Debashish Nandi, Aloke K. Dutta, and Yogesh Singh Chauhan, "Benchmarking of the BSIM-BULK for Cryo-CMOS Design", IEEE Electron Devices Technology and Manufacturing Conference (EDTM), Hong Kong, March 2025.

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4. Ateeb Naseer, Yawar Hayat Zarkob, Musaib Rafiq, Mohammad Sajid Nazir, Owais Ahmad, Amit Agarwal, Somnath Bhowmick, and Yogesh Singh Chauhan, "Enhancing the Capabilities of Quantum Transport Simulations Utilizing Machine Learning Strategies", MLCAD '24: Proceedings of the 2024 ACM / IEEE International Symposium on Machine Learning for CAD, September 2024.   

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5. Yawar Hayat Zarkob, Ayushi Sharma, Girish Pahwa, Debashish Nandi, Chetan K. Dabhi, Volker Kubrak, Bob Peddenpohl, Mingchun Tang, Chenming Hu, and Yogesh Singh Chauhan, "Compact Modeling and Experimental Validation of Reverse Mode Impact Ionization in LDMOS Transistors within the BSIM-BULK Framework", IEEE Electron Devices Technology and Manufacturing Conference (EDTM), March 2024.   

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6. Ayushi Sharma, Shivendra Singh Parihar, Yawar Hayat Zarkob, Weike Wang, Kimiko Imura, Praveen Diwedi, and Yogesh Singh Chauhan, "Characterization and Experimental Validation of Self Heating in RF LDMOS Transistor using BSIM-BULK Model", IEEE Electron Devices Technology and Manufacturing Conference (EDTM), March 2024.   

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7. Mohammad Sajid Nazir, Ahtisham Pampori, Yawar Hayat Zarkob, Anirban Kar, and Yogesh Singh Chauhan, "Characterization and Modeling of I-V, C-V and Trapping behaviour of SiC Power MOSFETs", IEEE Electron Devices Technology and Manufacturing Conference (EDTM), Seoul, Korea, March 2023.

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8. Ayushi Sharma, Yawar Hayat Zarkob, Ravi Goel, Chetan K. Dabhi, Girish Pahwa, Chenming Hu, and Yogesh Singh Chauhan, "Recent Enhancements in the Standard BSIM-BULK MOSFET Model", IEEE International Conference on Emerging Electronics (ICEE), Bengaluru, Dec. 2022.

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9. Yawar Hayat Zarkob, Shazan Ahmad Bhat, Sheikh Aamir Ahsan, "Analytical Surface Potential Calculation for Organic Thin-film Transistors", IEEE International Semiconductor Conference (CAS), Romania, Oct. 2021. { Supplementary Material } (My B. Tech Final year Project Report, Chapter 4)

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Miscellaneous:

1. I independently derived the bulk charge expression with poly depletion effect (major portion), which featured as Appendix 5.A (pp. 110–132) for "Chapter 5 (BSIM-BULK Charge and Capacitance Model)" in the book "BSIM-Bulk MOSFET Model for IC Design - Digital, Analog, RF and High-voltage", Woodhead Publishing, 2023.
2. I led the development of the following BSIM-BULK releases:

 

I presented the Phase 2 cadidate model presentation for IITK-SiC model at 2025 CMC Q4 held at Synopsys Headquarters in Sunnyvale, California.  New

Hosted the EE Research Day 2025 at IIT Kanpur.

Presented my two papers at International Compact Modeling Conference (ICMC), CA, USA, 2025.

Presented my poster titled, "Compact Modeling and Experimental Validation of Reverse Mode Impact Ionization in LDMOS Transistors within the BSIM-BULK Framework", in the IEEE Electron Devices Technology and Manufacturing Conference (EDTM), Seoul, Korea, March, 2024.

Presented my paper titled, "Analytical Surface Potential Calculation for Organic Thin-film Transistors", in the 44th edition of IEEE International Semiconductor Conference (CAS), Romania, 6-8 October, 2021.

Co-presented the demonstration of project titled, "An implementation of an industrial internet of things on an SMT assembly line", with Gaurav Bhandari, in 2020 International Conference on COMmunication Systems & NETworkS (COMSNETS), Bengaluru, as part of my internship.