Submitted Work:
  1. Yawar Hayat Zarkob, Mohammad Sajid Nazir, Ateeb Naseer, Ahtisham Pampori, Chetan K. Dabhi, Zhu Chaosong, Leang Sern Ee, Chenming Hu, and Yogesh Singh Chauhan, "Characterization and Modeling of Flicker Noise in Bulk MOSFETs down to Sub-Threshold Regime", submitted to Solid State Electronics.   NEW
  2. Arka Chakraborty, Musaib Rafiq, Yawar Hayat Zarkob, Yogesh Singh Chauhan, and Shubham Sahay, "Ferroelectric FET based Bayesian Inference Engine for Disease Diagnosis", IEEE Transactions on Circuits and Systems - I (under revision), (TechRxiv Preprint 2023)
Journal Publications:
  1. Ayushi Sharma, Yawar Hayat Zarkob, Girish Pahwa, Chetan K. Dabhi, Ravi Goel, Harshit Agarwal, Volker Kubrak, Mingchun Tang, Maximilian Treiber, Chenming Hu, and Yogesh Singh Chauhan, "Compact Modeling of Impact Ionization and Conductivity Modulation in LDMOS Transistors", IEEE Transactions on Electron Devices, 2024.   NEW
Conference Publications:
  1. Yawar Hayat Zarkob, Ayushi Sharma, Girish Pahwa, Debashish Nandi, Chetan K. Dabhi, Volker Kubrak, Bob Peddenpohl, Mingchun Tang, Chenming Hu, and Yogesh Singh Chauhan, "Compact Modeling and Experimental Validation of Reverse Mode Impact Ionization in LDMOS Transistors within the BSIM-BULK Framework", IEEE Electron Devices Technology and Manufacturing Conference (EDTM), March 2024.   
  2. Mohammad Sajid Nazir, Ahtisham Pampori, Yawar Hayat Zarkob, Anirban Kar, and Yogesh Singh Chauhan, "Characterization and Modeling of I-V, C-V and Trapping behaviour of SiC Power MOSFETs", IEEE Electron Devices Technology and Manufacturing Conference (EDTM), Seoul, Korea, March 2023.
  3. Ayushi Sharma, Yawar Hayat Zarkob, Ravi Goel, Chetan K. Dabhi, Girish Pahwa, Chenming Hu, and Yogesh Singh Chauhan, "Recent Enhancements in the Standard BSIM-BULK MOSFET Model", IEEE International Conference on Emerging Electronics (ICEE), Bengaluru, Dec. 2022.
  4. Yawar Hayat Zarkob, Shazan Ahmad Bhat, Sheikh Aamir Ahsan, "Analytical Surface Potential Calculation for Organic Thin-film Transistors", IEEE International Semiconductor Conference (CAS), Romania, Oct. 2021. { Supplementary Material } (My B. Tech Final year Project Report, Chapter 4)
Miscellaneous:
  1. I wrote Appendix 5.A (pp. 110–132) for "Chapter 5 (BSIM-BULK Charge and Capacitance Model)" in the book "BSIM-Bulk MOSFET Model for IC Design - Digital, Analog, RF and High-voltage", Woodhead Publishing, 2023.
  2. I led the development of the following BSIM-BULK releases:
 
 

My compact model releases:

  • BSIM-BULK 107.2.0 (2024).

    • Presentations/Demonstrations:

  • Presented my paper titled, "Analytical Surface Potential Calculation for Organic Thin-film Transistors", in the 44th edition of IEEE International Semiconductor Conference (CAS), Romania, 6-8 October, 2021.
  • Co-presented the demonstration of project titled, "An implementation of an industrial internet of things on an SMT assembly line", with Gaurav Bhandari, in 2020 International Conference on COMmunication Systems & NETworkS (COMSNETS), Bengaluru, as part of my internship.

    • Dissertation:

  • "B.Tech Final Year Project Report", July. 2021.