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Books:
1. Title: Industry Standard FDSOI Compact Model BSIM-IMG For IC Design
Authors: Chenming Hu, Sourabh Khandelwal, Yogesh S. Chauhan, Thomas Mckay, Juan Pablo Duarte, Pragya Kushwaha, Harshit Agarwal

2. Title: FinFET Modeling for IC Simulation and Design: Using the BSIM-CMG Standard
Authors: Yogesh S. Chauhan, Darsen Lu, Sriram Venugopalan, Sourabh Khandelwal, Juan P. Duarte, Navid Paydavosi, Ali M. Niknejad, and Chenming Hu

3. Title: POWER/HVMOS Devices Compact Modelling (contributed a chapter)
Editor: Wladyslaw Grabinski and Thomas Gneiting

Publications: Check publications on Researchgate and Google Scholar.
  • Google Scholar Link
  • Google Scholar Profile of Yogesh Chauhan

    2021:
      Journal Articles:
    1. D. Rajasekharan, A. Gaidhane, A. R. Trivedi, and Y. S. Chauhan, "Ferroelectric FET-based Implementation of FitzHugh-Nagumo Neuron Model", under revision in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2021.
    2. N. Pandey, K. Qureshi and Y. S. Chauhan, "Variability Analysis in a 3-D Multi-Granular HfxZr1-xO2 Ferroelectric Capacitor", under revision in IEEE Transactions on Electron Devices, 2021.
    3. C. K. Dabhi, A. S. Roy, L. Yang and Y. S. Chauhan, "Anomalous GIDL Effect with Back Bias in FinFET: Physical Insights and Compact Modeling", under revision in IEEE Transactions on Electron Devices, 2021.
    4. A. U. H. Pampori, S. A. Ahsan, R. Dangi, U. Goyal, S. K. Tomar, M. Mishra and Y. S. Chauhan, "Modeling of Bias Dependent Effective Velocity and its Impact on Saturation Transconductance in AlGaN/GaN HEMTs", IEEE Transactions on Electron Devices, 2021.
    5. R. Goel, C. Gupta, M. Skalsky and Y. S. Chauhan, "Analysis and Modeling of Anomalous Flicker Noise in Long Channel Halo MOSFETs", Solid State Electronics, 2021.
    6. S. Salamin, G. Zervakis, F. Klemme, H. Kattan, Y. S. Chauhan, J. Henkel, and H. Amrouch, "Impact of NCFET Technology on Eliminating the Cooling Cost and Boosting the Efficiency of Google TPU", IEEE Transactions on Computers, 2021.
    7. R. Goel, W. Wang, and Y. S. Chauhan, "Improved Modeling of Flicker Noise Including Velocity Saturation Effect in FinFETs and Experimental Validation", Microelectronic Journal, 2021.
    8. Ashok P, Y. S. Chauhan, and A. Verma, "Effect of Vanadium Thickness and Deposition Temperature on VO2 Synthesis using Atmospheric Pressure Thermal Oxidation", Thin Solid Films, Vol. 724, art. no. 138630, April 2021.
    9. O. Prakash, G. Pahwa, C. K. Dabhi, Y. S. Chauhan, and H. Amrouch, "Impact of Self-Heating on Negative-Capacitance FinFET: Device-Circuit Interaction", IEEE Transactions on Electron Devices, Vol. 68, Issue 4, April 2021.
    10. G. Paim, G. Zervakis, G. Pahwa, Y. S. Chauhan, E. A. C. Costa, S. Bampi, J. Henkel, and H. Amrouch, "On the Resiliency of NCFET Circuits against Voltage Over-Scaling", IEEE Transactions on Circuits and Systems I, Vol. 68, Issue 4, April 2021.
    11. G. Zervakis, I. Anagnostopoulos, S. Salamain, Y. S. Chauhan, J. Henkel, and H. Amrouch, "Impact of NCFET on Neural Network Accelerators", IEEE Access, Vol. 9, pp. 43748 - 43758, 2021.
    12. G. Pahwa, A. Gaidhane, A. Agarwal, and Y. S. Chauhan, "Assessing Negative-Capacitance Drain-Extended Technology for High-Voltage Switching and Analog Applications", IEEE Transactions on Electron Devices, Vol. 68, Issue 2, Feb. 2021.
    13. P. Dwivedi, R. Singh, and Y. S. Chauhan, "Crossing the Nernst Limit (59 mV/pH) of Sensitivity Through Tunneling Transistor Based Biosensor", IEEE Sensors Journal, Vol. 21, Issue 3, Feb. 2021.
    14. Conference Papers:
    15. R. Goel and Y. S. Chauhan, "Compact Modeling of Flicker Noise in High Voltage MOSFETs and Experimental Validation", IEEE Latin America Electron Devices Conference (LAEDC), April 2021.
    16. O. Prakash, C. Dabhi, Y. Chauhan, and H. Amrouch, "Transistor Self-Heating: The Rising Challenge for Semiconductor Testing", IEEE VLSI Test Symposium (VTS’21), April 2021.
    17. V. M. V. Santen, S. Thomann, Y. Chauhan, J. Henkel, and H. Amrouch, "Reliability-Driven Voltage Optimization for NCFET-based SRAM Memory Banks", IEEE VLSI Test Symposium (VTS’21), April 2021.
    18. O. Prakash, A. Gupta, G. Pahwa, Y. S. Chauhan, and H. Amrouch, "On the Critical Role of Ferroelectric Thickness for Negative Capacitance Transistor Optimization", IEEE Electron Devices Technology and Manufacturing Conference (EDTM), Chengdu, China, Mar. 2021.
    19. G. Bajpai, A. Gupta, O. Prakash, Y. S. Chauhan, and H. Amrouch, "Soft Errors in Negative Capacitance FDSOI SRAMs", IEEE Electron Devices Technology and Manufacturing Conference (EDTM), Chengdu, China, Mar. 2021.

    2020:
      Journal Articles:
    1. J. Knechtel, S. Patnaik, M. Nabeel, M. Ashraf, Y. S. Chauhan, J. Henkel, O. Sinanoglu, and H. Amrouch, "Power Side-Channel Attacks in Negative Capacitance Transistor (NCFET)", IEEE Micro, Vol. 40, Issue 6, Nov.-Dec. 2020.
    2. O. Prakash, G. Pahwa, Y. S. Chauhan and H. Amrouch, "Impact of Interface Traps on Negative Capacitance Transistor: Device and Circuit Reliability", IEEE Journal of Electron Devices Society, Vol. 8, Nov. 2020.
    3. K. Nandan, C. Yadav, P. Rastogi, A. T.-Lopez, A. M.-Sanchez, E. G. Marin, F. G. Ruiz, S. Bhowmick, and Y. S. Chauhan, "Compact Modeling of Multi-layered MoS2 FETs including Negative Capacitance Effect", IEEE Journal of Electron Devices Society, Vol. 8, Nov. 2020.
    4. A. D. Gaidhane, G. Pahwa, A. Dasgupta, A. Verma, and Y. S. Chauhan, "Compact Modeling of Surface Potential, Drain Current and Terminal Charges in Negative Capacitance Nanosheet FET including Quasi-Ballistic Transport", IEEE Journal of Electron Devices Society, Vol. 8, Nov. 2020.
    5. C. Gupta, S. Dey, R. Goel, C. Hu, and Y. S. Chauhan, "Modeling of Current Mismatch and 1/f Noise for Halo Implanted Drain-Extended MOSFETs", IEEE Transactions on Electron Devices, Vol. 67, Issue 11, Nov. 2020.
    6. N. Pandey and Y. S. Chauhan, "Analytical Modeling of Short Channel Effects in MFIS Negative Capacitance FET including Quantum Confinement Effects", IEEE Transactions on Electron Devices, Vol. 67, Issue 11, Nov. 2020.
    7. S. Agnihotri, A. Agarwal, S. Bhowmick, and Y. S. Chauhan, "Exploration of High Symmetry β-PxSiy Materials for 2D-electronics", Proceedings of the Indian National Science Academy (PINSA), Vol. 86, Issue 3, Oct. 2020.
    8. D. Rajasekharan, P. Kushwaha, and Y. S. Chauhan, "Associative Processing using Negative Capacitance FDSOI Transistor for Pattern Recognition", Microelectronics Journal, Vol. 104, art. no. 104877, Oct. 2020.
    9. H. Amrouch, G. Pahwa, A. D. Gaidhane, C. K. Dabhi, F. Klemme, O. Prakash and Y. S. Chauhan, "Impact of Variability on Processor Performance in Negative Capacitance FinFET Technology", IEEE Transactions on Circuits and Systems I, Vol. 67, Issue 9, Sep. 2020.
    10. C. K. Dabhi, S. S. Parihar, A. Dasgupta, and Y. S. Chauhan, "Compact Modeling of Negative-Capacitance FDSOI FETs for Circuit Simulations", IEEE Transactions on Electron Devices, Vol. 67, Issue 7, July 2020.
    11. Ashok P, Y. S. Chauhan, and A. Verma, "Vanadium Dioxide Thin Films Synthesized Using Low Thermal Budget Atmospheric Oxidation", Thin Solid Films,Vol. 706, art. no. 138003, July 2020.
    12. Ashok P, Y. S. Chauhan, and A. Verma, "High Infrared Reflectance Modulation in VO2 Films Synthesized on Glass and ITO coated Glass substrates using Atmospheric Oxidation of Vanadium", Optical Materials, 110, art. no. 110438, July 2020.
    13. F. Bellando, C. K. Dabhi, A. Saeidi, C. Gastaldi, Y. S. Chauhan, and A. M. Ionescu, "Subthermionic Negative Capacitance Ion Sensitive Field-Effect Transistor", Applied Physics Letters, Vol. 116, Issue 17, April 2020.
    14. A. D. Gaidhane, G. Pahwa, A. Verma, and Y. S. Chauhan, "Gate Induced Drain Leakage in Negative Capacitance FinFETs", IEEE Transactions on Electron Devices, Vol. 67, Issue 3, March 2020.
    15. A. Dasgupta, S. S. Parihar, H. Agarwal, P. Kushwaha, Y. S. Chauhan and C. Hu, "Compact Model for Geometry Dependent Mobility in Nanosheet FETs", IEEE Electron Device Letters, Vol. 41, Issue 3, March 2020.
    16. A. Dasgupta, S. S. Parihar, P. Kushwaha, H. Agarwal, M.-Y. Kao, S. Salahuddin, Y. S. Chauhan and C. Hu, "BSIM Compact Model of Quantum Confinement in Advanced Nanosheet FETs", IEEE Transactions on Electron Devices, Vol. 66, Issue 2, pp. 730-737, Feb. 2020.
    17. Conference Papers:
    18. A. Rathi, M. Kumar, J. K. Verma, H. S. Jatana, Y. S. Chauhan, and Abhisek Dixit, "Modeling of 0.18µm RF Bulk and SOI Planar MOSFETs using Industry Standard BSIM Models", IEEE International Conference on Emerging Electronics (ICEE), Delhi, Nov. 2020.
    19. A. Dutta, D. Rajasekharan, and Y. S. Chauhan, "Compact Model Parameter Extraction Using Modular Q Learning for Nano-Scale Transistors", IEEE International Conference on Emerging Electronics (ICEE), Delhi, Nov. 2020.
    20. F. Klemme, Y. Chauhan, J. Henkel, and H. Amrouch, "Cell Library Characterization using Machine Learning for Design Technology Co-Optimization", IEEE International Conference on Computer-Aided Design (ICCAD), Paris, France, Nov. 2020.
    21. G. Bajpai, A. Gupta, O. Prakash, G. Pahwa, J. Henkel, Y. S. Chauhan, and H. Amrouch, "Impact of Radiation on Negative Capacitance FinFET", IEEE International Reliability Physics Symposium (IRPS), Grapevine-Texas, USA, Mar.-Apr. 2020.
    22. A. D. Gaidhane, G. Pahwa, A. Dasgupta, A. Verma, and Y. S. Chauhan, "Compact Modeling of Negative Capacitance Nanosheet FET including Quasi-Ballistic Transport", IEEE Electron Devices Technology and Manufacturing Conference (EDTM), Penang, Malaysia, Mar. 2020.
    23. J. K. Verma and Y. S. Chauhan, "Investigation of Standard and Enclosed Gate n-MOSFET Degradation due to Total Ionizing Dose Using BSIM-BULK", IEEE Electron Devices Technology and Manufacturing Conference (EDTM), Penang, Malaysia, Mar. 2020.
    24. R. Goel, C. Gupta, and Y. S. Chauhan, "Analysis and Compact Modeling of Thermal Noise in Halo Implanted MOSFETs", IEEE Electron Devices Technology and Manufacturing Conference (EDTM), Penang, Malaysia, Mar. 2020.
    25. O. Prakash, A. Gupta, G. Pahwa, J. Henkel, Y. S. Chauhan and H. Amrouch, "Impact of Interface Traps Induced Degradation on Negative Capacitance FinFET", IEEE Electron Devices Technology and Manufacturing Conference (EDTM), Penang, Malaysia, Mar. 2020.
    26. K. Nandan, C. Yadav, P. Rastogi, A. T.-Lopez, A. M.-Sanchez, E. G. Marin, F. G. Ruiz, S. Bhowmick, and Y. S. Chauhan, "Compact Modeling of Surface Potential and Drain Current in Multi-layered MoS2 FETs", IEEE Electron Devices Technology and Manufacturing Conference (EDTM), Penang, Malaysia, Mar. 2020.
    27. H. Agarwal, P. Kushwaha, A. Dasgupta, M.-Y. Kao, T. Morshed, G. Workman, K. Shanbhag, X. Li, Y. S. Chauhan, S. Salahuddin, C. Hu, "BSIM-IMG: Advanced Model for FDSOI Transistors with Back Channel Inversion", IEEE Electron Devices Technology and Manufacturing Conference (EDTM), Penang, Malaysia, Mar. 2020.
    28. H. Amrouch, V. M. Van Santen, G. Pahwa, Y. S. Chauhan, J. Henkel, "NCFET to Rescue Technology Scaling: Opportunities and Challenges", IEEE Asia and South Pacific Design Automation Conference (ASP-DAC), Beijing, China, Jan. 2020.

    2019:
      Journal Articles:
    1. H. Agarwal, C. Gupta, R. Goel, P. Kushwaha, Y.-K. Lin, M.-Y. Kao, J.-P Duarte, H.-L. Chang, Y. S. Chauhan, S. Salahuddin, and C. Hu, "BSIM-HV: High Voltage MOSFET Model Including Quasi-Saturation and Self-Heating Effect", IEEE Transactions on Electron Devices, Vol. 66, Issue 10, pp. 4258-4263, Oct. 2019.
    2. S. Tomar, B. Ghosh, S. Mardanya, P. Rastogi, B. S. Bhadoria, Y. S. Chauhan, A. Agarwal, and S. Bhowmick, "Intrinsic magnetism in monolayers of transition metal trihalides: a comparative study", Journal of Magnetism and Magnetic Materials, Vol. 489, pp. 165384, Nov. 2019.
    3. C. K. Dabhi, A. S. Roy, and Y. S. Chauhan, "Compact Modeling of Temperature Dependent Gate-Induced-Drain-Leakage Including Low Field Effects", IEEE Transactions on Electron Devices, Vol. 66, Issue 7, pp. 2892-2897, July 2019.
    4. H. Amrouch, S. Salamin, G. Pahwa, A. D. Gaidhane, J. Henkel, and Y. S. Chauhan, "Unveiling the Impact of IR-drop on Performance Gain in NCFET-based Processors", IEEE Transactions on Electron Devices, Vol. 66, Issue 7, pp. 3215-3223, July 2019.
    5. S. Agnihotri, M. Kumar, Y. S. Chauhan, A. Agarwal, and S. Bhowmick, "Interlayer decoupling in twisted bilayers of β-phosphorus and arsenic", FlatChem, Vol. 16, pp. 100112, July 2019.
    6. C. Gupta, H. Agarwal, R. Goel, C. Hu, and Y. S. Chauhan, "Improved Modeling of Bulk Charge Effect for BSIM-BULK Model", IEEE Transactions on Electron Devices, Vol. 66, Issue 6, pp. 2850-2853, June 2019.
    7. G. Pahwa, A. Agarwal, and Y. S. Chauhan, "Numerical Investigation of Short Channel Effects in Negative Capacitance MFIS and MFMIS Transistors: Above-Threshold Behavior", IEEE Transactions on Electron Devices, Vol. 66, Issue 3, pp. 1591–1598, Mar. 2019.
    8. M. Bhoir, Y. S. Chauhan and N. R. Mohapatra, "Back-gate Bias and Substrate Doping Influenced Substrate Effect in UTBB FD-SOI MOS Transistors: Analysis and Optimization Guidelines", IEEE Transactions on Electron Devices, Vol. 66, Issue 2, pp. 861-867, Feb. 2019.
    9. C. Gupta, N. Mohamed, H. Agarwal, R. Goel, C. Hu, and Y. S. Chauhan, "Accurate and Computationally Efficient Modeling of Nonquasi Static Effects in MOSFETs for Millimeter Wave Applications", IEEE Transactions on Electron Devices, Vol. 66, Issue 1, pp. 44-51, Jan. 2019.
    10. Thirunavukkarasu A, H. Amrouch, J. Joe, N. Goel, N. Parihar, S. Mishra, C. K. Dabhi, Y. S. Chauhan, J. Henkel, and S. Mahapatra, "A Device to Circuit Framework for Activity Dependent NBTI Aging in Digital Circuits", IEEE Transactions on Electron Devices, Vol. 66, Issue 1, pp. 316-323, Jan. 2019.
    11. S. Khandelwal, Y. S. Chauhan, T. A. Fjeldly, S. Ghosh, A. Pampori, D. Mahajan, R. Dangi, and S. A. Ahsan, "ASM GaN: Industry Standard Model for GaN RF and Power Devices - Part-I: DC, CV, and RF Model", IEEE Transactions on Electron Devices, Vol. 66, Issue 1, pp. 80-86, Jan. 2019.
    12. S. A. Albahrani, D. Mahajan, J. Hodges, Y. S. Chauhan, and S. Khandelwal, "ASM GaN: Industry Model for GaN RF and Power Devices - Part-II: Modeling of Charge Trapping", IEEE Transactions on Electron Devices, Vol. 66, Issue 1, pp. 87-94,Jan. 2019.
    13. A. Dasgupta, A. Verma, and Y. S. Chauhan, "Analysis and Compact Modeling of Insulator-Metal-Transition Material based PhaseFET Including Hysteresis and Multi-domain Switching", IEEE Transactions on Electron Devices, Vol. 66, Issue 1, pp. 169-176,Jan. 2019.
    14. S. Mishra, H. Amrouch, J. Joe, C. K. Dabhi, K. Thakor, Y. S. Chauhan, J. Henkel, and S. Mahapatra, "A Simulation Study of NBTI Impact on 14nm node FinFET Technology for Logic Applications: Device Degradation to Circuit Level Interaction", IEEE Transactions on Electron Devices, Vol. 66, Issue 1, pp. 271-278, Jan. 2019.
    15. Conference Papers:
    16. G. Joshi, Y. S. Chauhan, and A. Verma, "Growth and Characterization of β-Ga2O3 Thin Films using Low Pressure Chemical Vapor Deposition", International Workshop on Physics of Semiconductor Devices (IWPSD), Kolkata, India, Dec. 2019.
    17. Ashok P., Y. S. Chauhan, and A. Verma, "Vanadium Dioxide Thin Films with High Infra-Red Reflectance Modulation on Glass Substrate", International Conference on Optics and Optoelectronics (ICOL-2019), Dehradun, India, Oct. 2019.
    18. Ashok P., Y. S. Chauhan, and A. Verma, "Electrically and Optically Switching Vanadium Dioxide Thin Films Synthesized Using Low Thermal Budget Atmospheric Oxidation", International Workshop on Oxide Electronics, Kyoto, Japan, Oct. 2019.
    19. P. Kushwaha, H. Agarwal, A. Dasgupta, Y. K. Lin, M-Y. Kao, Y. S. Chauhan, S. Salahuddin, and C. Hu, "Modeling the Quantum Gate capacitance of Nano-Sheet Gate-All-Around MOSFET", IEEE SOI–3D–Subthreshold Microelectronics Technology Unified Conference (S3S), San Francisco, USA, Oct. 2019.
    20. C. K. Dabhi, P. Kushwaha, H. Agarwal, S. S. Chauhan, C. Hu, and Y. S. Chauhan, "Physical Analysis of Non-monotonic DIBL Dependence on Back Gate Bias in Thick Front Gate Oxide FDSOI MOSFETs", IEEE SOI–3D–Subthreshold Microelectronics Technology Unified Conference (S3S), San Francisco, USA, Oct. 2019.
    21. G. Pahwa, A. Agarwal and Y. S. Chauhan, "Evaluating Negative Capacitance Technology for RF MOS Varactors", IEEE SOI–3D–Subthreshold Microelectronics Technology Unified Conference (S3S), San Francisco, USA, Oct. 2019.
    22. K. Sharma, A. D. Gaidhane and Y. S. Chauhan, "Performance Enhancement of 4T-IFGC DRAM in 7nm NC-FinFET Technology Node", IEEE SOI–3D–Subthreshold Microelectronics Technology Unified Conference (S3S), San Francisco, USA, Oct. 2019.
    23. H. Amrouch, G. Pahwa, J. Henkel and Y. S. Chauhan, "NCFET-Aware Voltage Scaling", IEEE International Symposium on Low Power Electronics and Design (ISLPED), Lausanne, Switzerland, July 2019.
    24. M. Rapp, H. Amrouch, S. Salamin, G. Pahwa, J. Henkel and Y. S. Chauhan, "Performance, Power and Cooling Trade-Offs with NCFET-based Many-Cores", IEEE Design Automation Conference (DAC), Las Vegas, USA, June 2019.
    25. C. Gupta, R. Goel, H. Agarwal, C. Hu, and Y. S. Chauhan, "BSIM-BULK: Accurate Compact Model for Analog and RF Circuit Design", IEEE Custom Integrated Circuits Conference (CICC), Austin, USA, April 2019. (Invited)
    26. J. K. Verma, S. Ghosh, A. Yadav and Y. S. Chauhan, "Simulation, Characterization and Parameter Extraction of Radiation Hardened MOSFET", IEEE International Conference on Modeling of Systems Circuits and Devices, Hyderabad, India, Feb. 2019.
    27. S. A. Ahsan, A Pampori, S. Ghosh, S. Khandelwal, and Y. S. Chauhan, "Impact of Via-Inductance on Stability Behavior of Large Gate-Periphery Multi-finger RF Transistors", IEEE International Conference on Modeling of Systems Circuits and Devices, Hyderabad, India, Feb. 2019.
    28. V. Kumar, C. K. Dabhi, S. S. Parihar and Y. S. Chauhan, "Analysis and Compact Modeling of Drain-Extended FinFET", IEEE International Conference on Modeling of Systems Circuits and Devices, Hyderabad, India, Feb. 2019.
    29. A. D. Gaidhane, G. Pahwa, A. Verma, and Y. S. Chauhan, "Modeling of Inner Fringing Charges and Short Channel Effects in Negative Capacitance MFIS Transistor", IEEE Electron Devices Technology and Manufacturing Conference (EDTM), Singapore, Mar. 2019.
    30. D. Rajasekharan, A. R. Trivedi, and Y. S. Chauhan, "Neuromorphic Circuits on FDSOI Technology for Computer Vision Applications", IEEE International Conference on VLSI Design (VLSID), Delhi, India, Jan. 2018.

    2018:
      Journal Articles:
    1. A. K. Upadhyay, A. K. Kushwaha, P. Rastogi, Y. S. Chauhan, and S. K. Vishvakarma, "An Explicit Channel Charge, Backscattering and Mobility Model of Graphene FET in Quasi-Ballistic Regime", IEEE Transactions on Electron Devices, Vol. 65, Issue 12, pp. 5468-5474, Dec. 2018.
    2. U. K. Das, G. Eneman, R. S. R. Velampati, Y. S. Chauhan, K. B. Jinesh, and T. K. Bhattacharyya, "Consideration of UFET Architecture for the 5nm Node and Beyond Logic Transistor", IEEE Journal of the Electron Devices Society, Vol. 6, Issue 1, pp. 1129-1135, Dec. 2018.
    3. D. Rajasekharan, P. Kushwaha, S. S. Chauhan, and Y. S. Chauhan, "Non-Boolean Associative Processing using FDSOI MOSFET-based Inverter", IEEE Transactions on Nanotechnology, Vol. 17, Issue 6, pp. 1235-1242, Nov. 2018.
    4. S. Mishra, N. Parihar, Anandkrishnan R., C. K. Dabhi, Y. S. Chauhan, and S. Mahapatra, "NBTI Related Variability Impact on 14nm Node FinFET SRAM Performance and Static Power: Correlation to Time Zero Fluctuations", IEEE Transactions on Electron Devices, Vol. 65, Issue 11, pp. 4846-4853, Nov. 2018.
    5. G. Pahwa, A. Agarwal, and Y. S. Chauhan, "Numerical Investigation of Short Channel Effects in Negative Capacitance MFIS and MFMIS Transistors: Subthreshold Behavior", IEEE Transactions on Electron Devices, Vol. 65, Issue 11, pp. 5130-5136, Nov. 2018.
    6. H. Amrouch, G. Pahwa, A. D. Gaidhane, J. Henkel, and Y. S. Chauhan, "Negative Capacitance Transistor to Address the Fundamental Limitations in Technology Scaling: Processor Performance", IEEE Access, Vol. 6, Issue 1, pp. 52754-52765, Oct. 2018.
    7. C. Gupta, R. Goel and Y. S. Chauhan, "Analysis and Modeling of Current Mismatch in Laterally Non-Uniform MOSFETs", IEEE Transactions on Electron Devices, Vol. 65, Issue 10, pp. 4254-4262, Oct. 2018.
    8. C. Yadav, P. Rastogi, T. Zimmer, and Y. S. Chauhan, "Charge Based Modeling of Transition Metal Dichalcogenide Transistors Including Ambipolar, Trapping and Negative Capacitance Effects", IEEE Transactions on Electron Devices, Vol. 65, Issue 10, pp. 4202-4208, Oct. 2018.
    9. C. Gupta, S. Dey, H. Agarwal, R. Goel, C. Hu, and Y. S. Chauhan, "Analysis and Modeling of Temperature and Bias Dependence of Current Mismatch in Halo Implanted MOSFETs", IEEE Transactions on Electron Devices, Vol. 65, Issue 9, pp. 3608-3616, Sept. 2018.
    10. R. Singh, K. Aditya, S. S. Parihar, Y. S. Chauhan, R. Vega, T. B. Hook, and A. Dixit, "Evaluation of 10nm Bulk FinFET RF Performance - Conventional vs. NC-FinFET", IEEE Electron Device Letters, Vol. 39, Issue 8, pp. 1246-1249, Aug. 2018.
    11. C. K. Dabhi, A. Dasgupta, P. Kushwaha, H. Agarwal, C. Hu, and Y. S. Chauhan, "Modeling of Induced Gate Thermal Noise including Back Bias Effect in FD-SOI MOSFET", IEEE Microwave and Wireless Components Letters, Vol. 28, Issue 7, pp. 597-599, July 2018.
    12. P. Kushwaha, H. Agarwal, Y.-K. Lin, M.-Y. Kao, J.-P. Duarte, H.-L. Chang, W. Wong, J. Fan, Y. S. Chauhan, S. Salahuddin, and C. Hu, "Modeling of advanced RF Bulk FinFETs", IEEE Electron Device Letters, Vol. 39, Issue 6, pp. 791-794, June 2018.
    13. A. D. Gaidhane, G. Pahwa, A. Verma, and Y. S. Chauhan, "Compact Modeling of Drain Current, Charges and Capacitances in Long Channel Gate-All-Around Negative Capacitance MFIS Transistor", IEEE Transactions on Electron Devices, Vol. 65, Issue 5, pp. 2024-2032, May 2018.
    14. A. Priydarshi, Y. S. Chauhan, S. Bhowmick, and A. Agarwal, "Strain-tunable charge carrier mobility of atomically thin phosphorus allotropes", Physical Review B, Vol. 97, Issue 11, pp. 115434(1-8), March 2018.
    15. S. Tomar, P. Rastogi, B. S. Bhadoria, S. Bhowmick, Y. S. Chauhan, and A. Agarwal, "Adsorption of magnetic transition metals on borophene: an ab-initio study", European Physical Journal B, 91: 51, pp. 1-6, March 2018.
    16. A. Dasgupta, P. Rastogi, A. Agarwal, C. Hu, and Y. S. Chauhan, "Compact Modeling of Cross-Sectional Scaling in Gate-All-Around FETs: 3-D to 1-D Transition", IEEE Transactions on Electron Devices, Vol. 65, Issue 3, pp. 1094-1100, March 2018.
    17. G. Pahwa, T. Dutta, A. Agarwal, and Y. S. Chauhan, "Physical Insights on Negative Capacitance Transistors in Non-Hysteresis and Hysteresis Regimes: MFMIS vs MFIS Structures", IEEE Transactions on Electron Devices, Vol. 65, Issue 3, pp. 867-873, March 2018.
    18. S. Agnihotri, P. Rastogi, Y. S. Chauhan, A. Agarwal, and S. Bhowmick, "Significant Enhancement of the Stark Effect in Rippled Monolayer Blue Phosphorous", ACS Journal of Physical Chemistry C, 122 (9), pp. 5171-5177, Feb. 2018.
    19. Y.-K. Lin, P. Kushwaha, J. P. Duarte, H.-L. Chang, H. Agarwal, S. Khandelwal, A. B. Sachid, M. Harter, J. Watts, Y. S. Chauhan, S. Salahuddin, and C. Hu, "New Mobility Model for Accurate Modeling of Transconductance in FDSOI MOSFETs", IEEE Transactions on Electron Devices, Vol. 65, Issue 2, pp. 463-469, Feb. 2018.
    20. T. Dutta, G. Pahwa, A. Agarwal, and Y. S. Chauhan, "Impact of Process Variations on Negative Capacitance FinFET Devices and Circuits", IEEE Electron Device Letters, Vol. 39, Issue 1, pp. 147-150, Jan. 2018.
    21. Conference Papers:
    22. S. Tomar, P. Rastogi, B. S. Bhadoria, A. Agarwal, S. Bhowmick, and Y. S. Chauhan, "Thermoelectric Properties of CrI3 Monolayer", IEEE International Conference on Emerging Electronics (ICEE), Bengaluru, India, Dec. 2018.
    23. K. Qureshi, G. Pahwa, and Y. S. Chauhan, "Impact of Linear Intergranular Variation in Remnant Polarization on Negative Capacitance Field Effect Transistor", IEEE International Conference on Emerging Electronics (ICEE), Bengaluru, India, Dec. 2018.
    24. D. K. Singh, A. Dasgupta, A. K. Agarwal, and Y. S. Chauhan, "Incident Flux Based Monte Carlo Simulation of Silicon and GaAs FETs in Quasi-Ballistic regime", IEEE International Conference on Emerging Electronics (ICEE), Bengaluru, India, Dec. 2018.
    25. A. D. Gaidhane, G. Pahwa, A. Verma, and Y. S. Chauhan, "Compact Modeling of Drain Current in Double Gate Negative Capacitance MFIS Transistor", IEEE International Conference on Emerging Electronics (ICEE), Bengaluru, India, Dec. 2018.
    26. A. Dasgupta, P. Rastogi, D. Saha, A. Gaidhane, A. Agarwal and Y. S. Chauhan, "Modeling of Multi-domain Switching in Ferroelectric Materials: Application to Negative Capacitance FETs", IEEE International Electron Devices Meeting (IEDM), San Francisco, Dec. 2018.
    27. B. T. Vankayalapati, R. Nune, S. Anand, Y. S. Chauhan, M. Patel, "Comparison of Si and GaN Power Devices Based SMPS for Satellite Application", IEEE Power Electronics, Drives and Energy Systems Conference, Chennai, India, Dec. 2018.
    28. R. Goel, C. Gupta, and Y. S. Chauhan, "An Empirical Model to Enhance the Flexibility of gm/Id Tuning in BSIM-BULK Model", IEEE Uttar Pradesh Section International Conference on Electrical, Electronics and Computer Engineering (UPCON), Gorakhpur, India, Nov. 2018.
    29. S. Khandelwal, Y. Chauhan, J. Hodges, S. A. Albahrani, "Non-linear RF Modeling of GaN HEMTs with Industry Standard ASM GaN Model", IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS), San Diego, USA, Oct. 2018. (Invited)
    30. S. Khandelwal and Y. S. Chauhan, "ASM GaN: Industry Standard Compact Model for GaN Power and RF Devices", International Workshop on Power Supply On Chip (PwrSoC), Hsinchu, Taiwan, Oct. 2018,. (Invited)
    31. U. K. Das, G. Eneman, R. Shankar, R. Velampati, Y. S. Chauhan, K. B. Jinesh, T. K. Bhattacharya, "Consideration of UFET Architecture for the 5nm Node and Beyond Logic Transistor", Silicon Nanoelectronics Workshop (SNW). Honolulu, USA, June 2018.
    32. S. Ghosh, S. A. Ahsan, S. Khandelwal, A. Pampori, R. Dangi and Y. S. Chauhan, "ASM-HEMT: A Robust Physics-Based GaN HEMT Model for Power and RF Applications", Workshop on Compact Modeling (WCM), Anaheim, CA, USA, May 2018. (Invited)
    33. P. Kushwaha, J. P. Duarte, Y.-K. Lin, H. Agarwal, H.-L. Chang, Y. S. Chauhan, S. Salahuddin, and C. Hu, "Unified Compact Model for Gate All Around FETs - Nanosheets, Nanowires, Multi Bridge Channel MOSFETs", Workshop on Compact Modeling (WCM), Anaheim, CA, USA, May 2018. (Invited)
    34. S. Tomar, P. Rastogi, B. S. Bhadoria, A. Agarwal, S. Bhowmick, and Y. S. Chauhan, "Strain Dependent Carrier Mobility in 8−Pmmn Borophene: ab-initio study", IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT), Bengaluru, India, Mar. 2018.
    35. P. Kushwaha, H. Agarwal, C. K. Dabhi, Y.-K. Lin, J. P. Duarte, C. Hu, and Y. S. Chauhan, "A Unified Flicker Noise Model for FDSOI MOSFETs Including Back-bias Effect", IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT), Bengaluru, India, Mar. 2018.
    36. P. Rastogi, A. Dasgupta, and Y. S. Chauhan, "Diameter Scaling in III-V Gate-All-Around Transistor for Different Cross-Sections", IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT), Bengaluru, India, Mar. 2018. (Best Paper Award)
    37. P. Rastogi, S. Bhowmick, A. Agarwal, and Y. S. Chauhan, "Atomistic Study of Acoustic Phonon Limited Mobility in Extremely Scaled Si and Ge Films", IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT), Bengaluru, India, Mar. 2018.
    38. A. Pampori, S. A. Ahsan, S. Ghosh, S. Khandelwal, and Y. S. Chauhan, "Physics-based Compact Modeling of MSM-2DEG GaN-based Varactors for THz Applications", IEEE Electron Devices Technology and Manufacturing Conference (EDTM), Kobe, Japan, Mar. 2018.
    39. D. Rajasekharan, S. S. Chauhan, A. R. Trivedi, and Y. S. Chauhan, "Energy and Area Efficient Tunnel FET-based Spiking Neural Networks", IEEE Electron Devices Technology and Manufacturing Conference (EDTM), Kobe, Japan, Mar. 2018.

    2017:
      Journal Articles:
    1. M. D. Ganeriwala, C. Yadav, F. G. Ruiz, E. G. Marin, Y. S. Chauhan, N. R. Mohapatra, "Modeling of Quantum Confinement and Capacitance in III-V Gate-All-Around 1D Transistors", IEEE Transactions on Electron Devices, Vol. 64, Issue 12, pp. 4889-4896, Dec. 2017.
    2. S. A. Ahsan, A. Pampori, S. Ghosh, S. Khandelwal, and Y. S. Chauhan, "A New Small-signal Parameter Extraction Technique for large gate-periphery GaN HEMTs", IEEE Microwave and Wireless Components Letters, Vol. 27, Issue 10, pp. 918-920, Oct. 2017.
    3. S. A. Ahsan, S. Ghosh, S. Khandelwal, and Y. S. Chauhan, "Physics-based Multi-bias RF Large-Signal GaN HEMT Modeling and Parameter Extraction Flow", IEEE Journal of the Electron Devices Society, Vol. 5, Issue 5, pp. 310-319, Sept. 2017.
    4. T. Dutta, G. Pahwa, A. R. Trivedi, S. Sinha, A. Agarwal, and Y. S. Chauhan, "Performance Evaluation of 7 nm Node Negative Capacitance FinFET based SRAM", IEEE Electron Device Letters, Vol. 38, Issue 8, pp. 1161-1164, Aug. 2017.
    5. P. Jain, C. Yadav, P. Rastogi, A. Agarwal, and Y. S. Chauhan, "Surface Potential based Modeling of Charge, Current, and Capacitances in DGTFET including Mobile Channel Charge and Ambipolar Behaviour", Solid State Electronics, Vol. 134, pp. 74-81, Aug. 2017.
    6. C. Yadav, M. D. Ganeriwala, N. R. Mohapatra, A. Agarwal, and, Y. S. Chauhan, "Compact Modeling of Gate Capacitance in III-V Channel Quadruple-Gate FETs", IEEE Transactions on Nanotechnology, Vol. 16, Issue 4, pp. 703-710, Jul. 2017.
    7. P. Jain, P. Rastogi, C. Yadav, A. Agarwal, and Y. S. Chauhan, "Band-to-Band Tunneling in Γ valley for Ge Source Lateral Tunnel Field Effect Transistor: Thickness scaling", Journal of Applied Physics, Vol. 122, Issue 1, pp. 014502(1-7), Jul. 2017.
    8. B. Ghosh, P. Kumar, A. Thakur, Y. S. Chauhan, S. Bhowmick, and A. Agarwal, "Anisotropic plasmons, excitons and electron energy loss spectroscopy of phosphorene", Physical Review B, Vol. 96, Issue 3, pp. 35422, Jul. 2017.
    9. Y. Sahu, P. Kushwaha, A. Dasgupta, C. Hu, and Y. S. Chauhan, "Compact Modeling of Drain Current Thermal Noise in FDSOI MOSFETs Including Back-Bias Effect", IEEE Transactions on Microwave Theory and Techniques, Vol. 65, Issue 7, pp. 2261-2270, Jul. 2017.
    10. A. Dasgupta, A. Agarwal, and, Y. S. Chauhan, "An Improved Model for Quasi-Ballistic Transport in MOSFETs", IEEE Transactions on Electron Devices, Vol. 64, Issue 7, pp. 3032-3036, Jul. 2017.
    11. A. Dasgupta, A. Agarwal, and, Y. S. Chauhan, "Unified Compact Model for Nanowire Transistors including Quantum Effects and Quasi-ballistic Transport", IEEE Transactions on Electron Devices, Vol. 64, Issue 4, pp. 1837-1845, Apr. 2017.
    12. C. Gupta, H. Agarwal, Y. K. Lin, A. Ito, C. Hu and Y. S. Chauhan, "Analysis and Modeling of Zero-VTH Native Devices with Industry Standard BSIM6 Model", Japanese Journal of Applied Physics (Special Issue), Vol. 56, Issue 4S, pp. 04CD09(1-6), Apr. 2017.
    13. P. Rastogi, S. Kumar, S. Bhowmick, A. Agarwal, and Y. S. Chauhan, "Effective Doping of Monolayer Phosphorene by Surface Adsorption of Atoms for Electronic and Spintronic Applications", IETE Journal of Research, Vol. 63, Issue 2, pp. 205-215, Mar. - Apr. 2017. (IETE - S K MITRA MEMORIAL AWARD-2018)
    14. S. A. Ahsan, S. Ghosh, S. Khandelwal, and Y. S. Chauhan, "Pole-Zero Approach to Analyze and Model the Kink in Gain-Frequency Plot of GaN HEMTs", IEEE Microwave and Wireless Components Letters, Vol. 27, Issue 3, pp. 266-268, Mar. 2017.
    15. C. Yadav, M. Agrawal, A. Agarwal, and, Y. S. Chauhan, "Compact Modeling of Charge, Capacitance, and Drain Current in III-V Channel Double Gate FETs", IEEE Transactions on Nanotechnology, Vol. 16, Issue 2, pp. 347-354, Mar. 2017.
    16. S. A. Ahsan, S. Ghosh, S. Khandelwal, and Y. S. Chauhan, "Analysis and Modeling of Cross-Coupling and Substrate Capacitance in GaN HEMTs for Power-Electronic Applications", IEEE Transactions on Electron Devices (Special Issue), Vol. 64, Issue 3, pp. 816-823, Mar. 2017.
    17. G. Pahwa, T. Dutta, A. Agarwal, and Y. S. Chauhan, "Compact Model for Ferroelectric Negative Capacitance Transistor with MFIS Structure", IEEE Transactions on Electron Devices, Vol. 64, Issue 3, pp. 1366-1374, Mar. 2017.
    18. C. Yadav, A. Agarwal, and, Y. S. Chauhan, "Compact Modeling of Transition Metal Dichalcogenide based Thin body Transistors and Circuit Validation", IEEE Transactions on Electron Devices, Vol. 64, Issue 3, pp. 1261-1268, Mar. 2017.
    19. H. Agarwal, C. Gupta, S. Dey, S. Khandelwal, C. Hu, and Y. S. Chauhan, "Anomalous Transconductance in Long Channel Halo Implanted MOSFETs: Analysis and Modeling", IEEE Transactions on Electron Devices, Vol. 64, Issue 2, pp. 376-383, Feb. 2017.
    20. Conference Papers:
    21. S. Ghosh, S. A. Ahsan, S. Khandelwal, A. Pampori, R. Dangi, and Y. S. Chauhan, "Physics Based Analysis and Modeling of Capacitances in a Dual Field Plated Power GaN HEMT", International Workshop on Physics of Semiconductor Devices (IWPSD), Delhi, India, Dec. 2017.
    22. S. A. Ahsan, S. Ghosh, S. Khandelwal, A. Pampori, R. Dangi, and Y. S. Chauhan, "A Scalable Physics-based RF Large Signal Model for Multi-Finger GaN HEMTs", International Workshop on Physics of Semiconductor Devices (IWPSD), Delhi, India, Dec. 2017.
    23. D. Datta, H. Dixit, S. Agarwal, A. Dasgupta, M. Tran, D. Houssameddine, Y. S. Chauhan, D. Shum, and F. Benistant, "Quantitative Model for Switching Asymmetry in Perpendicular MTJ: A Material-Device-Circuit Co-Design", IEEE International Electron Devices Meeting (IEDM), San Francisco, Dec. 2017.
    24. S. Agnihotri, P. Rastogi, A. Agarwal, and Y. S. Chauhan, "Effect of Substitutional Mg Doping in In0.5Ga0.5N", IEEE Student Conference on Research and Development (SCOReD), Malaysia, Dec. 2017.
    25. S. Khandelwal, S. Ghosh, S. A. Ahsan and Y. S. Chauhan, "Dependence of GaN HEMT AM/AM and AM/PM Non-Linearity on AlGaN Barrier Layer Thickness", IEEE Asia Pacific Microwave Conference (APMC), Kuala Lumpur, Malaysia, Nov. 2017.
    26. S. A. Ahsan, S. Ghosh, S. Khandelwal and Y. S. Chauhan, "Surface-potential-based Gate-periphery-scalable Small-signal Model for GaN HEMTs", IEEE Compound Semiconductor IC Symposium (CSICS), Miami, USA, Oct. 2017.
    27. R. Singh, P. Kushwaha, S. Ghosh, B. Parvais, Y. S. C and A. Dixit, "Characterization and Modeling of N-Channel Bulk FinFETs from DC to High Frequencies", IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), Hsinchu, Taiwan, Oct. 2017.
    28. A. Dasgupta and Y. S. Chauhan, "Modeling of Flicker Noise in Quasi-ballistic FETs", IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Kamakura, Japan, Sep. 2017.
    29. M. Bhoir, P. Kushwaha, Y. S. Chauhan and N. R. Mohapatra, "Impact of Substrate on the Frequency Behavior of Trans-conductance in Ultra-thin Body and BOX FDSOI MOS Devices – A Physical Insight", IEEE International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Taiwan, Apr. 2017.
    30. C. Gupta, H. Agarwal, C. Hu, and Y. S. Chauhan, "Analysis and Modeling of Capacitances in Halo-Implanted MOSFETs", IEEE Electron Devices Technology and Manufacturing Conference (EDTM), Toyama, Japan, Feb.-Mar. 2017.
    31. A. Dasgupta, C. Gupta, A. Dutta, Y.-K. Lin, S. Srihari, T. Ethirajan, C. Hu, and Y. S. Chauhan, "Modeling of Body-bias Dependence of Overlap Capacitances in Bulk MOSFETs", IEEE International Conference on VLSI Design, Hyderabad, India, Jan. 2017.

    2016:
      Journal Articles:
    1. G. Pahwa, T. Dutta, A. Agarwal, S. Khandelwal, S. Salahuddin, C. Hu, and Y. S. Chauhan, "Analysis and Compact Modeling of Negative Capacitance Transistor with High ON-Current and Negative Output Differential Resistance - Part I, Model description", IEEE Transactions on Electron Devices, Vol. 63, Issue 12, pp. 4981-4985, Dec. 2016.
    2. G. Pahwa, T. Dutta, A. Agarwal, S. Khandelwal, S. Salahuddin, C. Hu, and Y. S. Chauhan, "Analysis and Compact Modeling of Negative Capacitance Transistor with High ON-Current and Negative Output Differential Resistance - Part II, Model validation", IEEE Transactions on Electron Devices, Vol. 63, Issue 12, pp. 4986-4992, Dec. 2016.
    3. A. Dasgupta, A. Agarwal, Sourabh Khandelwal and, Y. S. Chauhan, "Compact Modeling of Surface Potential, Charge and Current in Nanoscale Transistors under Quasi-Ballistic Regime", IEEE Transactions on Electron Devices, Vol. 63, Issue 11, pp. 4151-4159, Nov. 2016.
    4. P. Kushwaha, A. Dasgupta, Y. Sahu, S. Khandelwal, C. Hu, and Y. S. Chauhan, "Characterization of RF Noise in UTBB FD-SOI MOSFET", IEEE Journal of the Electron Devices Society, Vol. 4, Issue 6, pp. 379-386, Nov. 2016.
    5. M. D. Ganeriwala, C. Yadav, N. R. Mohapatra, S. Khandelwal, C. Hu, and Y. S. Chauhan, "Modeling of Charge and Quantum Capacitance in Low Effective Mass III-V FinFETs", IEEE Journal of the Electron Devices Society, Vol. 4, Issue 6, pp. 396-401, Nov. 2016.
    6. P. Kushwaha, S. Khandelwal, J. P. Duarte, C. Hu, and Y. S. Chauhan, "Thermal Resistance Modeling in FDSOI Transistors with Industry Standard Model BSIM-IMG", Elsevier Microelectronics Journal, Vol. 56, pp. 171-176, Oct. 2016.
    7. P. Kumar, Y. S. Chauhan, Amit Agarwal and, S. Bhowmick, "Thickness and Stacking Dependent Polarizability and Dielectric Constant of Graphene–Hexagonal Boron Nitride Composite Stacks", ACS Journal of Physical Chemistry C, Vol. 120, Issue 31, pp. 17620-17626, Aug. 2016.
    8. A. Dasgupta and Y. S. Chauhan, "Modeling of Induced Gate Thermal Noise in HEMTs", IEEE Microwave and Wireless Components Letters, Vol. 26, Issue 6, pp. 428-430, June 2016.
    9. P. Kushwaha, S. Khandelwal, J. P. Duarte, C. Hu, and Y. S. Chauhan, "RF Modeling of FDSOI transistors using Industry Standard BSIM-IMG Model", IEEE Transactions on Microwave Theory and Techniques, Vol. 64, Issue 6, pp. 1745-1751, June 2016.
    10. P. Kumar, B. S. Bhadoria, S. Kumar, S. Bhowmick, and Y. S. Chauhan, and Amit Agarwal, "Thickness and electric field dependent polarizability and dielectric constant in phosphorene", Physical Review B, Vol. 93, Issue 19, pp. 195428(1-8), May 2016.
    11. Y.-K. Lin, S. Khandelwal, A. Medury, H. Agarwal, H.-L. Chang, Y. S. Chauhan, and C. Hu, "Modeling of Sub-surface Leakage Current in Low Vth Short Channel MOSFET at Accumulation Bias", IEEE Transactions on Electron Devices, Vol. 63, Issue 5, pp. 1840-1845, May 2016.
    12. T. Dutta, P. Kumar, P. Rastogi, A. Agarwal, and Y. S. Chauhan, "Atomistic study of band structure and transport in extremely thin channel InP MOSFETs", Physica Status Solidi A (Special issue), Vol 213, Issue 4, pp. 898-904, April 2016.
    13. B. K. Kompala, P. Kushwaha, H. Agarwal, S. Khandelwal, J. P. Duarte, C. Hu and Y. S. Chauhan, "Modeling of Nonlinear Thermal Resistance in FinFETs", Japanese Journal of Applied Physics (Special Issue), Vol. 55, No. 4S, pp. 04ED11(1-5), March 2016.
    14. A. Ojha, Y. S. Chauhan, and N. Mohapatra, "A Channel Stress-Profile based Compact Model for Thereshold Voltage prediction of Uniaxial Strained HKMG nMOS Transistors", IEEE Journal of the Electron Devices Society, Vol. 4, Issue 2, pp. 42-49, March 2016.
    15. T. Dutta, S. Kumar, P. Rastogi, A. Agarwal, and Y. S. Chauhan, "Impact of Channel Thickness Variation on Bandstructure and Source-to-Drain Tunneling in Ultra-Thin Body III-V MOSFETs", IEEE Journal of the Electron Devices Society, Vol. 4, Issue 2, pp. 66-71, March 2016.
    16. S. A. Ahsan, S. Ghosh, A. Dasgupta, K. Sharma, S. Khandelwal, and Y. S. Chauhan, "Capacitance Modeling in Dual Field Plate Power GaN HEMT for Accurate Switching Behaviour", IEEE Transactions on Electron Devices, Vol. 63, Issue 2, pp. 565-572, Feb. 2016.
    17. S. Khandelwal, H. Agarwal, P. Kushwaha, J. P. Duarte, A. Medury, Y. S. Chauhan, S. Salahuddin, and C. Hu, "Unified Compact Model Covering Drift-Diffusion to Ballistic Carrier Transport", IEEE Electron Device Letters, Vol. 37, Issue 2, pp. 134-137, Feb. 2016.
    18. H. Agarwal, P. Kushwaha, C. Gupta, S. Khandelwal, C. Hu, and Y. S. Chauhan, "Analysis and Modeling of Flicker Noise in Lateral Asymmetric Channel MOSFETs", Solid State Electronics, Vol. 115, Part A, pp. 33-38, Jan. 2016.
    19. Conference Papers:
    20. S. Ghosh, S. A. Ahsan, A. Dasgupta, S. Khandelwal, and Y. S. Chauhan, "GaN HEMT Modeling for Power and RF Applications using ASM-HEMT", IEEE International Conference on Emerging Electronics (ICEE), Mumbai, India, Dec. 2016.
    21. G. Pahwa, T. Dutta, A. Agarwal, and Y. S. Chauhan, "Energy-Delay Tradeoffs in Negative Capacitance FinFET based CMOS Circuits", IEEE International Conference on Emerging Electronics (ICEE), Mumbai, India, Dec. 2016. (Best Paper Award)
    22. T. Dutta, B. S. Syamalaraju, S. Bhowmick, Amit Agarwal, and Y. S. Chauhan, "Performance Projection of Mono and Multi-Layer Silicane FETs in the Ballistic Limit", IEEE International Conference on Emerging Electronics (ICEE), Mumbai, India, Dec. 2016.
    23. N. Mohamed, H. Agarwal, C. Gupta, and Y. S. Chauhan, "Compact Modeling of NQS Effect in Bulk MOSFETs for RF Circuit Design in Sub-THz Regime", IEEE International Conference on Emerging Electronics (ICEE), Mumbai, India, Dec. 2016.
    24. D. K. Singh, A. Dasgupta, and Y. S. Chauhan, "Accurate Modeling of Centroid Shift in III-V FETs including Non-linear Potential Profile and Wave-function Penetration", IEEE International Conference on Emerging Electronics (ICEE), Mumbai, India, Dec. 2016.
    25. H. Agarwal, C. Gupta, S. Khandelwal, C. Hu, S. Dey, K. Chan and Y. S. Chauhan, "Analysis and Modeling of Low Frequency Noise in Presence of Doping Non-Uniformity in MOSFETs", IEEE International Conference on Emerging Electronics (ICEE), Mumbai, India, Dec. 2016.
    26. S. Ghosh, A. Dasgupta, A. K. Dutta, S. Khandelwal, and Y. S. Chauhan, "Physics based Modeling of Gate Current including Fowler-Nordheim Tunneling in GaN HEMT", IEEE International Conference on Emerging Electronics (ICEE), Mumbai, India, Dec. 2016.
    27. P. Jain, P. Rastogi, T. Dutta, A. Agarwal, and Y. S. Chauhan, "Impact of Thickness Scaling on Vertical and Lateral Tunneling in Ge Source Tunnel FETs", IEEE International Conference on Emerging Electronics (ICEE), Mumbai, India, Dec. 2016.
    28. S. A. Ahsan, S. Ghosh, S. Khandelwal, and Y. S. Chauhan, "Statistical Simulation for GaN HEMT Large Signal RF performance using a Physics-based Model", IEEE International Conference on Emerging Electronics (ICEE), Mumbai, India, Dec. 2016.
    29. A. Dasgupta, H. Agarwal, A. Agarwal, and Y. S. Chauhan, "Modeling of Flicker Noise in Quasi-ballistic devices", IEEE International Conference on Emerging Electronics (ICEE), Mumbai, India, Dec. 2016.
    30. Dinesh R., T. Dutta, A. R. Trivedi, and Y. S. Chauhan, "Energy-Efficient Spiking Neural Networks based on Tunnel FET", IEEE International Conference on Emerging Electronics (ICEE), Mumbai, India, Dec. 2016.
    31. C. K. Dabhi, A. Dasgupta, and Y. S. Chauhan, "Computationally efficient Analytical Surface Potential model for UTBB FD-SOI Transistors", IEEE International Conference on Emerging Electronics (ICEE), Mumbai, India, Dec. 2016.
    32. C. K. Dabhi, P. Kushwaha, A. Dasgupta, H. Agarwal, and Y. S. Chauhan, "Impact of Back Plane Doping on RF Performance of FD-SOI Transistor using Industry Standard BSIM-IMG Model", IEEE International Conference on Emerging Electronics (ICEE), Mumbai, India, Dec. 2016.
    33. A. Dasgupta, S. Ghosh, S. A. Ahsan, S. Khandelwal, N. Defrance, and Y. S. Chauhan, "Modeling DC, RF and Noise behavior of GaN HEMTs using ASM-HEMT Compact Model", IEEE International Microwave and RF Conference (IMaRC), Delhi, India, Dec. 2016.
    34. S. A. Ahsan, S. Ghosh, A. Dasgupta, S. Khandelwal, and Y. S. Chauhan, "ASM-HEMT: Advanced SPICE Model for Gallium Nitride High Electron Mobility Transistors", International Conference of Young Researchers on Advanced Materials (ICYRAM), Bangalore, India, Dec. 2016.
    35. C. Gupta, H. Agarwal, Y. K. Lin, S. Khandelwal, Akira Ito, C. Hu, and Y. S. Chauhan, "Analysis and Modeling of Zero-VTH Devices with Industry Standard BSIM6 Model", International Conference on Solid State Devices and Materials (SSDM2016), Tsukuba, Japan, September 2016.
    36. G. Pahwa, T. Dutta, A. Agarwal, and Y. S. Chauhan, "Designing Energy Efficient and Hysteresis Free Negative Capacitance FinFET with Negative DIBL and 3.5X ION using Compact Modeling Approach", IEEE European Solid-State Device Research Conference (ESSDERC), Lausanne, Switzerland, Sept. 2016. (Invited)
    37. S. Ghosh, S. A. Ahsan, S. Khandelwal and Y. S. Chauhan, "Modeling of Source/Drain Access Resistances and their Temperature Dependence in GaN HEMTs", IEEE Conference on Electron Devices and Solid-State Circuits (EDSSC), Hong Kong, Aug. 2016.
    38. S. A. Ahsan, S. Ghosh, S. Khandelwal and Y. S. Chauhan, "Modeling of Kink-Effect in RF Behaviour of GaN HEMTs using ASM-HEMT Model", IEEE Conference on Electron Devices and Solid-State Circuits (EDSSC), Hong Kong, Aug. 2016.
    39. C. Gupta, H. Agarwal, R. Gillon, S. Khandelwal, Y.-K. Lin, C. Hu and Y. S. Chauhan, "Modeling of High Voltage LDMOSFET using Industry Standard BSIM6 MOS Model", IEEE Conference on Electron Devices and Solid-State Circuits (EDSSC), Hong Kong, Aug. 2016.
    40. P. Kushwaha, R. Agarwal, H. Agarwal, S. Khandelwal, J. P. Duarte, Y.-K. Lin, H.-L. Chang, C. Hu and Y. S. Chauhan, "Modeling of Threshold Voltage for Operating Point using Industry standard BSIM-IMG Model", IEEE Conference on Electron Devices and Solid-State Circuits (EDSSC), Hong Kong, Aug. 2016.
    41. P. Kushwaha, H. Agarwal, M. Bhoir, N. R. Mohapatra, S. Khandelwal, J. P. Duarte, Y.-K. Lin, H.-L. Chang, C. Hu and Y. S. Chauhan, "Predictive Effective Mobility Model for FDSOI Transistors using Technology Parameters", IEEE Conference on Electron Devices and Solid-State Circuits (EDSSC), Hong Kong, Aug. 2016.
    42. H. Agarwal, P. Kushwaha, S. Khandelwal, J. P. Duarte, Y.-K. Lin, H.-L. Chang, C. Hu, H. Wu, P. D. Ye and Y. S. Chauhan, "Modeling of GeOI and Validation with Ge-CMOS Inverter Circuit using BSIM-IMG Industry Standard Model", IEEE Conference on Electron Devices and Solid-State Circuits (EDSSC), Hong Kong, Aug. 2016.
    43. R. Nune, A. Anurag, S. Anand and Y. S. Chauhan, "Comparative Analysis of Power Density in Si MOSFET and GaN HEMT based Flyback Converters", IEEE International Conference on Compatibility and Power Electronics, Bydgoszcz, Poland, June 2016.
    44. J. P. Duarte, S. Khandelwal, Y. S. Chauhan, and C. Hu, "Modeling Independent Multi-Gate MOSFET", Workshop on Compact Modeling, Washington DC, May 2016. (Invited)
    45. C. Yadav, A. Dutta, S. Sirohi, T. Ethirajan, and Y. S. Chauhan, "Unified Model for Sub-Bandgap and Conventional Impact Ionization in RF SOI MOSFETs with Improved Simulator Convergence", IEEE International Conference on VLSI Design, Kolkata, India, Jan. 2016.
    46. C. Yadav, A. Agarwal, and Y. S. Chauhan, "Analysis of Quantum Capacitance Effect in Ultra-Thin-Body III-V Transistor", IEEE International Conference on VLSI Design, Kolkata, India, Jan. 2016.

    2015:
      Journal Articles:
    1. C. Yadav, J. P. Duarte, S. Khandelwal, A. Agarwal, C. Hu, and Y. S. Chauhan, "Capacitance Modeling in III-V FinFETs", IEEE Transactions on Electron Devices, Vol. 62, Issue 11, pp. 3892-3897, Nov. 2015.
    2. P. Rastogi, T. Dutta, S. Kumar, A. Agarwal, Y. S. Chauhan, "Quantum Confinement Effects in Extremely Thin Body Germanium n-MOSFETs", IEEE Transactions on Electron Devices, Vol. 62, Issue 11, pp. 3575-3680, Nov. 2015.
    3. S. Khandelwal, H. Agarwal, J. P. Duarte, K. Chan, S. Dey, Y. S. Chauhan, and C. Hu, "Modeling STI Edge Parasitic Current for Accurate Circuit Simulations", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, Vol. 34, Issue 8, pp. 1291-1294, Aug. 2015.
    4. S. Khandelwal, J. P. Duarte, A. Medury, Y. S. Chauhan, S. Salahuddin, and C. Hu, "Modeling SiGe FinFETs with Thin Fin and Current Dependent Source/Drain Resistance", IEEE Electron Device Letters, Vol. 36, Issue 7, pp. 636-638, July 2015.
    5. A. Dasgupta, S. Khandelwal, and Y. S. Chauhan, "Surface potential based Modeling of Thermal Noise for HEMT circuit simulation", IEEE Microwave and Wireless Components Letters, Vol. 25, Issue 6, pp. 376-378, June 2015.
    6. H. Agarwal, S. Khandelwal, S. Dey, C. Hu, and Y. S. Chauhan, "Analytical Modeling of Flicker Noise in Halo Implanted MOSFETs", IEEE Journal of Electron Devices Society, Vol. 3, Issue 4, pp. 355-360, April 2015.
    7. H. Agarwal, C. Gupta, P. Kushwaha, C. Yadav, J. P. Duarte, S. Khandelwal, C. Hu, and Y. S. Chauhan, "Analytical Modeling and Experimental Validation of Threshold Voltage in BSIM6 MOSFET Model", IEEE Journal of the Electron Devices Society, Vol. 3, Issue 3, pp. 240,243, March 2015.
    8. P. Kushwaha, N. Paydavosi, S. Khandelwal, C. Yadav, H. Agarwal, J. P. Duarte, C. Hu, and Y. S. Chauhan, "Modeling the Impact of Substrate Depletion in FDSOI MOSFETs", Solid State Electronics, Vol. 104, Issue 2, pp. 6-11, Feb. 2015.
    9. S. Ghosh, A. Dasgupta, S. Khandelwal, S. Agnihotri, and Y. S. Chauhan, "Surface-Potential-Based Compact Modeling of Gate Current in AlGaN/GaN HEMTs", IEEE Transactions on Electron Devices, Vol. 62, Issue 2, pp. 443-448, Feb. 2015.
    10. Conference Papers:
    11. S. Agnihotri, S. Ghosh, A. Dasgupta, A. Ahsan, S. Khandewal, and Y. S. Chauhan, "Modeling of Trapping Effects in GaN HEMTs", IEEE India Conference (INDICON), New Delhi, India, Dec. 2015.
    12. C. Gupta, H. Agarwal, Akira Ito, S. Ghosh, P. Khushwaha, C. Hu, and Y. S. Chauhan, "Modeling of Zero-Vth MOSFET with Industry Standard BSIM6 Model", International Workshop on Physics of Semiconductor Devices (IWPSD), Bangalore, India, Dec. 2015.
    13. G. Pahwa, A. Agarwal, and Y. S. Chauhan, "Compact Modeling of Negative Capacitance Transistor with Experimental Validation", International Workshop on Physics of Semiconductor Devices (IWPSD), Bangalore, India, Dec. 2015.
    14. C. Yadav, A. Agarwal, and Y. S. Chauhan, "Compact Modeling of Charge Density and Capacitance in III-V channel Double Gate FETs", International Workshop on Physics of Semiconductor Devices (IWPSD), Bangalore, India, Dec. 2015.
    15. A. Dasgupta, A. Agarwal, and Y. S. Chauhan, "Compact Model for charge centroid in III-V FETs", International Workshop on Physics of Semiconductor Devices (IWPSD), Bangalore, India, Dec. 2015.
    16. S. Ghosh, S. Agnihotri, S. A. Ahsan, S. Khandelwal, and Y. S. Chauhan, "Analysis and Modeling of Trapping Effects in RF GaN HEMTs under Pulsed Conditions", International Workshop on Physics of Semiconductor Devices (IWPSD), Bangalore, India, Dec. 2015.
    17. S. Agnihotri, S. Ghosh, S. Khandelwal, and Y. S. Chauhan, "Impact of Gate Field Plate on DC, C-V, and Transient Characteristics of Gallium Nitride HEMTs", International Workshop on Physics of Semiconductor Devices (IWPSD), Bangalore, India, Dec. 2015.
    18. K. Sharma, S. Ghosh, A. Dasgupta, S. A. Ahsan, S. Khandelwal, and Y. S. Chauhan, "Capacitance Analysis of Field Plated GaN HEMT", International Workshop on Physics of Semiconductor Devices (IWPSD), Bangalore, India, Dec. 2015.
    19. A. Dasgupta, A. Agarwal, and Y. S. Chauhan, "Compact Modeling of Quasi-Ballistic transport in FETs", International Workshop on Physics of Semiconductor Devices (IWPSD), Bangalore, India, Dec. 2015.
    20. Y. Sahu, P. Kushwaha, J. P. Duarte, S. Khandelwal, C. Hu and Y. S. Chauhan, "Compact Modelling of Drain Current Thermal Noise in FDSOI MOSFETs", International Workshop on Physics of Semiconductor Devices (IWPSD), Bangalore, India, Dec. 2015.
    21. P. Kushwaha, S. Khandelwal, C. Hu and Y. S. Chauhan, "Recent Updates in Industry Standard BSIM-IMG Model for FDSOI Transistors", International Workshop on Physics of Semiconductor Devices (IWPSD), Bangalore, India, Dec. 2015.
    22. T. Dutta, M. Agrawal, A. Agarwal and Y. S. Chauhan, "Wavefunction Penetration Effects in Extremely Scaled III-V MOSFETs", International Workshop on Physics of Semiconductor Devices (IWPSD), Bangalore, India, Dec. 2015.
    23. N. Mohamed, H. Agarwal, C. Gupta, S. Khandelwal, C. Hu, and Y. S. Chauhan, "Scaling Capabilities of Industry-Standard BSIM6 MOSFET Model", International Workshop on Physics of Semiconductor Devices (IWPSD), Bangalore, India, Dec. 2015.
    24. H. Agarwal, S. Khandelwal, C. Hu, and Y. S. Chauhan, "Analysis and Modeling of Assymetric Channel MOSFET", International Workshop on Physics of Semiconductor Devices (IWPSD), Bangalore, India, Dec. 2015.
    25. S. A. Ahsan, S. Ghosh, J. Bandarupalli, S. Khandelwal, and Y. S. Chauhan, "Physics based large signal modeling for RF performance of GaN HEMTs", International Workshop on Physics of Semiconductor Devices (IWPSD), Bangalore, India, Dec. 2015.
    26. P. Rastogi, A. Agarwal, S. Bhowmick, and Y. S. Chauhan, "Doping Behavior via Adsorption in Monolayer Black Phosphorous", International Workshop on Physics of Semiconductor Devices (IWPSD), Bangalore, India, Dec. 2015.
    27. S. Khandelwal, S. Ghosh, Y. S. Chauhan, B. Iniguez, T. A. Fjeldly and C. Hu, "Surface-Potential-Based RF Large Signal Model for Gallium Nitride HEMTs", IEEE Compound Semiconductor IC Symposium (CSICS), New Orleans, USA, Oct. 2015.
    28. B. K. Kompala, P. Kushwaha, S. Khandelwal, J. P. Duarte, A. Medury, C. Hu, and Y. S. Chauhan, "Modeling of Nonlinear Thermal Resistance in FinFET", International Conference on Solid State Devices and Materials (SSDM2015), Sapporo, Japan, September 2015.
    29. J. P. Duarte, S. Khandelwal, A. Medury, C. Hu, P. Kushwaha, H. Agarwal, A. Dasgupta, and Y. S. Chauhan "BSIM-CMG: Standard FinFET Compact Model for Advanced Circuit Design", IEEE European Solid-State Circuit Conference (ESSCIRC), Graz, Austria, Sept. 2015. (Invited)
    30. P. Rastogi, T. Dutta, S. Kumar, A. Agarwal, Y. S. Chauhan, "Confinement Effects on Germanium Band-structure for UTB MOSFET", SRC TECHCON, Austin, USA, September 2015.
    31. P. Kushwaha, J. P. Duarte, S. Khandelwal, C. Hu, and Y. S. Chauhan, "Thermal Resistance Scaling with Number of fins in FinFET", SRC TECHCON, Austin, USA, September 2015.
    32. C. Yadav, A. Agarwal, Y. S. Chauhan, "Simulation study of gate capacitance with back bias effects in III-V UTB devices", SRC TECHCON, Austin, USA, September 2015.
    33. P. Kushwaha, H. Agarwal, S. Khandelwal, J. P. Duarte, A. Medury, C. Hu and Y. S. Chauhan, "BSIM-IMG: Compact Model for RF-SOI MOSFETs", IEEE Device Research Conference (DRC), Columbus, USA, June 2015.
    34. S. A. Ahsan, S. Ghosh, K. Sharma, A. Dasgupta, S. Khandelwal, and Y. S. Chauhan, "Capacitance Modeling of a GaN HEMT with Gate and Source Field Plates", IEEE International Symposium on Compound Semiconductors (ISCS), Santa Barbara, USA, June 2015.
    35. A. Dasgupta and Y. S. Chauhan, "Surface Potential Based Modeling of Induced Gate Thermal Noise for HEMTs", IEEE International Symposium on Compound Semiconductors (ISCS), Santa Barbara, USA, June 2015.
    36. S. Khandelwal, Y. S. Chauhan, B. Iniguez, and T. Fjeldly, "RF Large Signal Modeling of Gallium Nitride HEMTs with Surface-Potential Based ASM-HEMT Model", IEEE International Symposium on Compound Semiconductors (ISCS), Santa Barbara, USA, June 2015. (Invited)
    37. P. Rastogi, T. Dutta, S. Kumar, A. Agarwal, and Y. S. Chauhan, "First Principle Study of Quantization Effects on UTB InP MOSFET", IEEE International Symposium on Compound Semiconductors (ISCS), Santa Barbara, USA, June 2015.
    38. A. Dasgupta, S. Ghosh, S. Khandelwal, and Y. S. Chauhan, "ASM-HEMT: Compact model for GaN HEMTs", IEEE Conference on Electron Devices and Solid-State Circuits (EDSSC), Singapore, June 2015.
    39. K. Sharma, A. Dasgupta, S. Ghosh, S. A. Ahsan, S. Khandelwal, and Y. S. Chauhan, "Effect of Access Region and Field Plate on Capacitance behavior of GaN HEMT", IEEE Conference on Electron Devices and Solid-State Circuits (EDSSC), Singapore, June 2015.
    40. S. Khandelwal, J. P. Duarte, A. Medury, Y. S. Chauhan, and C. Hu, "New Industry Standard FinFET Compact Model for Future Technology Nodes", IEEE VLSI Technology symposium, Kyoto, June 2015.

    2014:
      Journal Articles:
    1. P. Rastogi, S. Kumar, S. Bhowmick, A. Agarwal, and Y. S. Chauhan, "Doping Strategies for Monolayer MoS2 via Surface Adsorption: A Systematic Study", ACS Journal of Physical Chemistry C, Vol. 118, pp. 30309-30314, Dec. 2014.
    2. A. Dasgupta, S. Khandelwal, and Y. S. Chauhan, "Compact Modeling of Flicker Noise in HEMTs", IEEE Journal of the Electron Devices Society, Vol. 2, Issue 6, pp. 174-178, Nov. 2014.
    3. C. Yadav, P. Kushwaha, S. Khandelwal, J. P. Duarte, Y. S. Chauhan, and C. Hu, "Modeling of GaN based Normally-off FinFET", IEEE Electron Device Letters, Vol. 35, Issue 6, pp. 612-614, June 2014.
    4. S. Khandelwal, J. P. Duarte, Y. S. Chauhan, and C. Hu, "Modeling 20nm Germanium FinFET with the Industry Standard FinFET Model", IEEE Electron Device Letters, Vol. 35, Issue 7, pp. 711-713, July 2014.
    5. Y. S. Chauhan, S. Venugopalan, M.-A. Chalkiadaki, M. A. Karim, H. Agarwal, S. Khandelwal, N. Paydavosi, J. P. Duarte, C. C. Enz, A. M. Niknejad, and C. Hu, "BSIM6: Analog and RF Compact Model for Bulk MOSFET", IEEE Transactions on Electron Devices, Vol. 61, Issue 2, pp. 234-244, Feb. 2014. (Invited)
    6. Conference Papers:
    7. P. Kushwaha, C. Yadav, H. Agarwal, J. Srivatsava, S. Khandelwal, J. P. Duarte, C. Hu, and Y. S. Chauhan, "BSIM-IMG with Improved Surface Potential Calculation Recipe", IEEE India Conference (INDICON), Pune, India, Dec. 2014. (Best Paper Award)
    8. C. Yadav, P. Kushwaha, H. Agarwal, and Y. S. Chauhan, "Threshold Voltage Modeling of GaN Based Normally-Off Tri-gate Transistor", IEEE India Conference (INDICON), Pune, India, Dec. 2014.
    9. S. Ghosh, K. Sharma, S. Khandelwal, S. Agnihotri, T. A. Fjeldly, F. M. Yigletu, B. Iniguez, and Y. S. Chauhan, "Modeling of Temperature Effects in a Surface-Potential Based ASM-HEMT model", IEEE International Conference on Emerging Electronics (ICEE), Bangalore, India, Dec. 2014.
    10. P. Rastogi, S. Kumar, A. Agarwal, and Y. S. Chauhan, "Ab-initio study of doping versus adatom in monolayer MoS2", IEEE International Conference on Emerging Electronics (ICEE), Bangalore, India, Dec. 2014.
    11. A. Dasgupta, C. Yadav, P. Rastogi, A. Agarwal, and Y. S. Chauhan, "Analysis and Modeling of Quantum Capacitance in III-V Transistors", IEEE International Conference on Emerging Electronics (ICEE), Bangalore, India, Dec. 2014. (Best Poster Award)
    12. Y. S. Chauhan, P. Kushwaha, S. Khandelwal, C. Yadav, N. Paydavosi, J. P. Duarte, and C. Hu, "BSIMIMG: COMPACT MODEL FOR UTBBSOI MOSFETs", Workshop on Compact Modeling (WCM), Washington D.C., USA, June 2014. (Invited)
    13. S. Khandelwal, J. P. Duarte, N. Paydavosi, Y. S. Chauhan, J. J. Gu, M. Si, P. D. Ye, and C. Hu, "InGaAs FinFET Modeling Using Industry Standard Compact Model BSIM-CMG", Workshop on Compact Modeling (WCM), Washington D.C., USA, June 2014.
    14. A. Dutta, S. Sirohi, T. Ethirajan, H. Agarwal, Y. S. Chauhan, and R. Q Williams, "BSIM6 - Benchmarking the Next Generation MOSFET Model for RF Applications", IEEE International Conference on VLSI Design, Mumbai, India, Jan. 2014.

    2013:
      Journal Articles:
    1. S. Khandelwal, C. Yadav, S. Agnihotri, Y. S. Chauhan, A. Curutchet, T. Zimmer, J.-C. Dejaeger, N. Defrance and T. A. Fjeldly, "A Robust Surface-Potential-Based Compact Model for GaN HEMT IC Design", IEEE Transactions on Electron Devices, Vol. 60, Issue 10, pp. 3216-3222, Oct. 2013.
    2. N. Paydavosi, S. Venugopalan, Y. S. Chauhan, J. P. Duarte, S. Jandhyala, A. M. Niknejad, and C. Hu, "BSIM - SPICE Models Enable FinFET and UTB IC Designs", IEEE Access, Vol. 1, pp. 1527-1539, May 2013.
    3. S. Khandelwal, S. Sharma, Y. S. Chauhan, T. Gneiting, and T. A. Fjeldly, "Modeling and Simulation Methodology for SOA Aware Circuit Design in DC and Pulsed-Mode Operation of HV MOSFETs", IEEE Transactions on Electron Devices, Vol. 60, Issue 2, pp. 714-718, Feb. 2013.
    4. Conference Papers:
    5. J. R. Sahoo, H. Agarwal, C. Yadav, P. Kushwah, S. Khandewal, R. Gillon, and Y. S. Chauhan, "High Voltage LDMOSFET Modeling using BSIM6 as Intrinsic-MOS Model", IEEE PrimeAsia, Visakhapatnam, Dec. 2013. (Gold Leaf Certificate)
    6. S. Agnihotri, S. Ghosh, A. Dasgupta, S. Khandewal, and Y. S. Chauhan, "A Surface Potential based Model for GaN HEMTs", IEEE PrimeAsia, Visakhapatnam, Dec. 2013. (Gold Leaf Certificate)
    7. H. Agarwal, S. Venugopalan, M. Chalkiadaki, N. Paydavosi, J. P. Duarte, S. Agnihotri, C. Yadav, P. Kushwaha, Y. S. Chauhan, C. C. Enz, A. Niknejad and C. Hu, "Recent Enhancements in BSIM6 Bulk MOSFET Model", IEEE International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), Glasgow, Scotland, Sept. 2013.
    8. Y. S. Chauhan, S. Venugopalan, N. Paydavosi, P. Kushwaha, S. Jandhyala, J. P. Duarte, S. Agnihotri, C. Yadav, H. Agarwal, A. Niknejad, and C. Hu, "BSIM Compact MOSFET Models for SPICE Simulation", IEEE International Conference Mixed Design of Integrated Circuits and Systems (MIXDES), Gdynia, Poland, June 2013. (Invited)

    2012:
      Journal Articles:
    1. S. Khandelwal, Y. S. Chauhan, and T. A. Fjeldly, "Analytical Modeling of Surface-Potential and Intrinsic Charges in AlGaN/GaN HEMT Devices", IEEE Transactions on Electron Devices, Vol 59, Issue 10, 2856-2860, Oct. 2012.
    2. M. A. Karim, Y. S. Chauhan, S. Venugopalan, A. B. Sachid, D. D. Lu, B.-Y. Nguyen, O. Faynot, A. M. Niknejad, and C. C. Hu, "Extraction of Isothermal Condition and Thermal Network in UTBB SOI MOSFETs", IEEE Electron Device Letters, Vol. 33, No. 9, pp. 1306-1308, Sept. 2012.
    3. S. Khandelwal, Y. S. Chauhan, D. D. Lu, S. Venugopalan, M. A. Karim, A. B. Sachid, B.-Y. Nguyen, O. Rozeau, O. Faynot, A. M. Niknejad, and C. C. Hu, "BSIM-IMG: A Compact Model for Ultra-Thin Body SOI MOSFETs with Back-Gate Control", IEEE Transactions on Electron Devices, Vol. 59, Issue 8, pp. 2019-2026, Aug. 2012.
    4. Conference Papers:
    5. C. Hu, A. Niknejad, Sriramkumar V., D. Lu, Y. S. Chauhan, M. Karim, A. Sachid, "BSIM-IMG: A Turnkey compact model for fully depleted technologies", IEEE International SOI Conference, Napa, USA, Oct. 2012. (Invited)
    6. M.-A. Chalkiadaki, A. Mangla, C. C. Enz, Y. S. Chauhan, M. A. Karim, S. Venugopalan, A. Niknejad, and C. Hu, "Evaluation of the BSIM6 Compact MOSFET Modelʹs Scalability in 40nm CMOS Technology", IEEE European Solid-State Device Research Conference (ESSDERC), Bordeaux, France, Sept. 2012.
    7. Y. S. Chauhan, S. Venugopalan, M. A. Karim, S. Khandelwal, N. Paydavosi, P. Thakur, A. M. Niknejad, and C. C. Hu, "BSIM - Industry Standard Compact MOSFET Models", IEEE European Solid-State Device Research Conference (ESSDERC), Bordeaux, France, Sept. 2012. Slides (Invited)
    8. Y. S. Chauhan, M. A. Karim, S. Venugopalan, S. Khandelwal, P. Thakur, N. Paydavosi, A. B. Sachid, A. Niknejad, and C. Hu, "BSIM6: Symmetric Bulk MOSFET Model", Workshop on Compact Modeling (WCM), Santa Clara, USA, June 2012. (Invited)
    9. S. Khandelwal, Y. S. Chauhan, M. A. Karim, S. Venugopalan, A. Sachid, A. Niknejad, and C. Hu, "Analytical Surface Potential Calculation in UTBSOI MOSFET with Independent Back-Gate Control", Workshop on Compact Modeling (WCM), Santa Clara, USA, June 2012.
    10. S. Khandelwal, Y. S. Chauhan, M. A. Karim, S. Venugopalan, A. Sachid, A. Niknejad, and C. Hu, "Analysis and Modeling of Vertical Non-uniform Doping in Bulk MOSFETs for Circuit Simulations", IEEE International Caribbean Conference on Devices, Circuits and Systems (ICCDCS), Playa del Carmen, Mexico, March 2012.

    2011:
      Conference Papers:
    1. S. Venugopalan, Y. S. Chauhan, D. D. Lu, M. A. Karim, A. M. Niknejad, and C. Hu, "Modeling Intrinsic and Extrinsic Asymmetry of 3D Cylindrical Gate/ Gate-All-Around FETs for Circuit Simulations", IEEE Non-Volatile Memory Technology Symposium (NVMTS), Shanghai, China, Nov. 2011.
    2. Y. S. Chauhan, D. D. Lu, S. Venugopalan, M. A. Karim, A. Niknejad, and C. Hu, "Compact Models for sub-22nm MOSFETs", Workshop on Compact Modeling (WCM), Boston, USA, June 2011. (Invited)
    3. M. A. Karim, S. Venugopalan, Y. S. Chauhan, D. Lu, A. Niknejad, and C. Hu, "Drain Induced Barrier Lowering (DIBL) Effect on the Intrinsic Capacitances of Nano-Scale MOSFETs", Workshop on Compact Modeling (WCM), Boston, USA, June 2011.

    2010:
      Conference Papers:
    1. S. Parthasarathy, A. Trivedi, S. Sirohi, R. Groves, M. Carroll, D. Kerr, A. Tombak, P. Mason, and Y. S. Chauhan, "RF SOI Switch FET Design and Modeling tradeoffs for GSM Applications", IEEE International Conference on VLSI Design, Bangalore, India, Jan. 2010.

    2008:
      Journal Articles:
    1. K. Akarvardar, H.S. Philip Wong, C. Eggimann, D. Tsamados, Y. S. Chauhan, and A. M. Ionescu, "Analytical Modeling of the Suspended-Gate FET and Design Insights for Low Power Logic", IEEE Transactions on Electron Devices, Vol. 55, No. 1, pp. 48-59, Jan. 2008.
    2. D. Tsamados, Y. S. Chauhan, C. Eggimann, K. Akarvardar, H.S. Philip Wong, and A. M. Ionescu, "Finite element analysis and analytical simulations of Suspended Gate-FET for ultra-low power inverters", Solid State Electronics, Vol. 52, Issue 9, pp. 1374-1381, Sept. 2008.
    3. Y. S. Chauhan, R. Gillon, M. Declercq, and A. M. Ionescu, "Impact of Lateral Nonuniform Doping and Hot Carrier Injection on Capacitance Behavior of High Voltage MOSFETs", IETE Technical Review, Vol. 25, Issue 5, pp. 244-250, Sept.-Oct 2008.
    4. A. Rusu, M. Mazza, Y. S. Chauhan, and A. M. Ionescu, "Oscillator Based on Suspended Gate MOS Transistors", Romanian Journal of Information Science and Technology, Vol. 11, No. 4, pp. 423-433, 2008.
    5. Conference Papers:
    6. Y. S. Chauhan, D. Tsamados, N. Abele, C. Eggimann, M. Declercq, and A. M. Ionescu, "Compact Modeling of Suspended Gate FET", IEEE International Conference on VLSI Design, Hyderabad, India, Jan. 2008. (Honorable Mention Award)

    2007:
      Journal Articles:
    1. Y. S. Chauhan, F. Krummenacher, R. Gillon, B. Bakeroot, M. Declercq, and A. M. Ionescu, "Compact Modeling of Lateral Non-uniform doping in High-Voltage MOSFETs", IEEE Transactions on Electron Devices, Vol. 54, No. 6, pp. 1527-1539, June 2007.
    2. Y. S. Chauhan, R. Gillon, B. Bakeroot, F. Krummenacher, M. Declercq, and A. M. Ionescu, "An EKV-based High Voltage MOSFET Model with improved mobility and drift model", Solid State Electronics, Vol. 51, Issues 11-12, pp. 1581-1588, Nov.-Dec. 2007. (Invited)
    3. Conference Papers:
    4. A. Rusu, M. Mazza, Y. S. Chauhan, and A. M. Ionescu, "MHz Oscillator based on Vibrating Gate MOS Transistor", IEEE International Semiconductor Conference, Sinaia, Romania, Oct. 2007.
    5. D. Tsamados, Y. S. Chauhan, C. Eggimann, K. Akarvardar, H.S. Philip Wong, and A. M. Ionescu, "Numerical and analytical simulations of Suspended Gate - FET for ultra-low power inverters", IEEE European Solid-State Device Research Conference (ESSDERC), Munich, Germany, Sept. 2007.
    6. Y. S. Chauhan, R. Gillon, M. Declercq, and A. M. Ionescu, "Impact of Lateral Non-uniform doping and hot carrier degradation on Capacitance behavior of High Voltage MOSFETs", IEEE European Solid-State Device Research Conference (ESSDERC), Munich, Germany, Sept. 2007.
    7. D. Tsamados, Y. S. Chauhan, C. Eggimann, and A. M. Ionescu, "Suspended-gate FET as a sleep transistor for ultra-low stand-by power applications", ACM Proceedings of the 2nd international conference on Nano-Networks (Nano-Net), Catania, Italy, Sept. 2007.
    8. K. Akarvardar, C. Eggimann, D. Tsamados, Y. Chauhan, A. M. Ionescu, and H.S. Philip Wong, "Analytical Modeling of the Suspended-Gate FET and Design Insights for Digital Logic", IEEE Device Research Conference (DRC), Bend, USA, June 2007.
    9. W. Grabinski, T. Grasser, G. Gildenblat, G. Smit, M. Bucher, A. C. T. Aarts, A. Tajic, Y. S. Chauhan, A. Napieralski, T. A. Fjeldly, B. Iniguez, G. Iannaccone, M. Kayal, W. Posch, G. Wachutka, F. Pregaldiny, C. Lallement, and L. Lemaitre, "MOS-AK: Open Compact Modeling Forum", International Workshop on Compact Modeling (IWCM), Yokohama, Japan, Jan. 2007.
    10. Y. S. Chauhan, F. Krummenacher, R. Gillon, B. Bakeroot, M. Declercq, and A. M. Ionescu, "A New Charge based Compact Model for Lateral Asymmetric MOSFET and its application to High Voltage MOSFET Modeling", IEEE International Conference on VLSI Design, Banglore, India, Jan. 2007.

    2006:
      Journal Articles:
    1. Y. S. Chauhan, C. Anghel, F. Krummenacher, C. Maier, R. Gillon, B. Bakeroot, B. Desoete, S. Frere, A. Baguenier Desormeaux, A. Sharma, M. Declercq, and A. M. Ionescu,"Scalable General High Voltage MOSFET Model including Quasi-Saturation and Self-Heating effect", Solid State Electronics, Vol. 50, Issues 11-12, pp. 1801-1813, Nov.-Dec. 2006.
    2. C. Anghel, B. Bakeroot, Y. S. Chauhan, R. Gillon, C. Maier, P. Moens, J. Doutreloigne, and A. M. Ionescu, "New Method for Threshold Voltage Extraction of High Voltage MOSFETs based on Gate-to-Drain Capacitance Measurement", IEEE Electron Device Letters, Vol. 27, No. 7, pp. 602-604, July 2006.
    3. Conference Papers:
    4. Y. S. Chauhan, F. Krummenacher, C. Anghel, R. Gillon, B. Bakeroot, M. Declercq, and A. M. Ionescu, "Analysis and Modeling of Lateral Non-Uniform Doping in High-Voltage MOSFETs", IEEE International Electron Devices Meeting (IEDM), San Francisco, USA, Dec. 2006. Slides
    5. A. S. Roy, Y. S. Chauhan, C. C. Enz, and J.-M. Sallesse, "Noise Modeling in Lateral Asymmetric MOSFET", IEEE International Electron Devices Meeting (IEDM), San Francisco, USA, Dec. 2006.
    6. Y. S. Chauhan, C. Anghel, F. Krummenacher, A. M. Ionescu, M. Declercq, R. Gillon, S. Frere, and B. Desoete,"A Highly Scalable High Voltage MOSFET Model", IEEE European Solid-State Device Research Conference (ESSDERC), Montreux, Switzerland, Sept. 2006. Slides
    7. A. S. Roy, Y. S. Chauhan, J.-M. Sallesse, C. C. Enz, A. M. Ionescu, and M. Declercq, "Partitioning Scheme in the Lateral Asymmetric MOST", IEEE European Solid-State Device Research Conference (ESSDERC), Montreux, Switzerland, Sept. 2006.
    8. Y. S. Chauhan, C. Anghel, F. Krummenacher, R. Gillon, A. Baguenier, B. Desoete, S. Frere, A. M. Ionescu, and M. Declercq, "A Compact DC and AC Model for Circuit Simulation of High Voltage VDMOS Transistor", IEEE International Symposium on Quality Electronic Design (ISQED), San Jose, USA, March 2006.

    2005:
      Conference Papers:
    1. C. Anghel, Y. S. Chauhan, N. Hefyene, and A. M. Ionescu, "A Physical Analysis of High Voltage MOSFET Capacitance Behaviour", IEEE International Symposium on Industrial Electronics (ISIE), Dubrovnik, Croatia, June 2005.

    2003:
      Conference Papers:
    1. B. Mazhari, and Y. S. Chauhan, "Design of current-Programmed amorphous-Silicon AMOLED Pixel Circuit", The 8th Asian Symposium on Information Display, China, 2003.
    2. B. Mazhari, and Y. S. Chauhan, "A New Negative Feedback based poly-Silicon AMOLED Pixel Circuit with Highly Linear Transfer Characteristics", 10th International Display Workshop, Fukuoka, Japan, 2003.

    Invited/Contributed Presentations:
    1. Y. S. Chauhan,"Physics and Modeling of FinFETand Nanosheet Transistors", TH Mittelhessen University of Applied Sciences, Germany, Mar. 2021.
    2. Y. S. Chauhan,"Physical Insights into the Operation of Negative Capacitance Transistors", Tezpur University, Feb. 2021.
    3. Y. S. Chauhan,"RF Wireless, 5G and GaN HEMT: Characte rization and Mode ling using ASM-HEMT", NIT Meghalaya, Feb. 2021.
    4. Y. S. Chauhan,"An introduction to RF Microelectronics", IIT Guwahati, Feb. 2021.
    5. Y. S. Chauhan,"GaN HEMT Characterization and Modeling using ASM-HEMT", IIT Guwahati, Feb. 2021.
    6. Y. S. Chauhan,"Physical Insights into the Operation of Negative Capacitance Transistors", IIT Indore, Dec. 2020.
    7. Y. S. Chauhan,"BSIM-BULK: Industry Standard SPICE Model for Analog, RF & High Voltage Applications", IEEE EDS Mini-Colloquim on Compact Modeling, URV Tarragona, Spain, Dec. 2020.
    8. Y. S. Chauhan,"Negative Capacitance Transistors - Modeling, Simulation and Processor Performance", IEEE International Conference on Emerging Electronics (ICEE), Delhi, India, Nov. 2020.
    9. Y. S. Chauhan,"GaN HEMT Characterization and Modeling using ASM-HEMT", NIT Silchar, October 2020.
    10. Y. S. Chauhan,"Ferroelectric Negative Capacitance Transistors for Emerging Technologies", IIT Patna, October 2020.
    11. A. Pampori and Y. S. Chauhan,"GaN HEMT Characterization and Modeling using ASM-HEMT", Keysight Design Forum, Tokyo, Japan, Sept. 2020.
    12. Y. S. Chauhan,"Physics and Modeling of Nano-Transistors", Jaypee Institute of Information Technology, July 2020.
    13. Y. S. Chauhan,"SPICE and Compact Modeling", Punjab Engineering College, June 2020.
    14. Y. S. Chauhan,"Physics and Modeling of Nano-Transistors", Punjab Engineering College, June 2020.
    15. Y. S. Chauhan,"ASM-HEMT GaN Model", International Microwave Symposium (IMS), Boston, USA, June 2019. Video
    16. Y. S. Chauhan,"Fundamentals and Recent Progress in Negative Capacitance Transistors", IEEE MOS-AK conference, Chengdu, China, June 2019.
    17. Y. S. Chauhan,"Negative Capacitance Transistors - Modeling, Simulation and Processor Performance", IEEE MOS-AK conference, Hyderabad, India, Feb. 2019.
    18. Y. S. Chauhan,"Negative Capacitance Transistors to Continue CMOS Scaling", IEEE EDS Distinguished Lecture, BUET Dhaka, Bangladesh, Dec. 2018.
    19. Y. S. Chauhan,"Atomistic Simulation and Compact Modeling of Atomically Thin Transistors", IEEE International Conference on Electrical and Computer Engineering (ICECE), Dhaka, Bangladesh, Dec. 2018.
    20. Y. S. Chauhan,"Modeling and Simulation of FinFET and Nanosheet Transistors", IEEE EDS Distinguished Lecture, Santa Clara, USA, Nov. 2018.
    21. Y. S. Chauhan,"Nanoscale Transistors for Integrated Circuits", UPCON, Madan Mohan Malviya University of Technology Gorakhpur, India, Nov. 2018.
    22. Y. S. Chauhan,"Physics and Modeling of Negative Capacitance Transistors", New York University, New York, USA, Sept. 2018.
    23. Y. S. Chauhan,"Negative Capacitance MOSFETs for Future Technology Nodes", Kalyani Engineering College, Kalyani, India, Jul. 2018.
    24. Y. S. Chauhan,"ASM-GaN: Industry Standard GaN HEMT Compact Model for Power-Electronics and RF Applications", Synopsys Users Group (SNUG), Bengaluru, India, Jul. 2018.
    25. Y. S. Chauhan,"Negative Capacitance Transistors - Physics, Modeling and Processor Performance at VDD = 0.4V", IEEE International Conference on Electronics, Computing and Communication Technologies (CONECCT), Bengaluru, India, Mar. 2018.
    26. Y. S. Chauhan,"Circuit Simulation and SPICE", Madan Mohan Malviya University of Technology Gorakhpur, India, Mar. 2018.
    27. Y. S. Chauhan,"Negative Capacitance MOSFETs for Future Technology Nodes", National Institute of Science and Technology, Behrampur, India, Feb. 2018.
    28. Y. S. Chauhan,"ASM-HEMT: Industry Standard Compact Model for GaN HEMTs", International Workshop on Physics of Semiconductor Devices (IWPSD), Delhi, India, Dec. 2017.
    29. Y. S. Chauhan,"Negative Capacitance MOSFETs for Future Technology Nodes", University of Calcutta, India, Nov. 2017.
    30. Y. S. Chauhan,"ASM-HEMT: Industry Standard Compact Modeling of GaN HEMTs for High Frequency and High Power Applications", NIT Silchar, India, Nov. 2017.
    31. Y. S. Chauhan,"SPICE and Compact Modeling", IIT-BHU, India, Jul. 2017.
    32. Y. S. Chauhan,"Compact Modeling of GaN HEMTs", SPIE lecture, IIT Roorkee, India, May 2017.
    33. Y. S. Chauhan,"Industry Standard Compact Modeling", IEEE Workshop on Compact Modeling, IIT Kanpur, India, Mar. 2017.
    34. Y. S. Chauhan,"Transistor Modeling for IC Design", University Institute of Engineering and Technology, Kanpur, India, Jan. 2017.
    35. Y. S. Chauhan,"Modeling of Nanoscale Transistors for IC Design", National Institute of Technology, Goa, India, Jan. 2017.
    36. C. Yadav and Y. S. Chauhan, "Modeling of Transition Metal Dichalcogenide Transistors for SPICE Simulation", MOS-AK Workshop, Berkeley, USA, Dec. 2016.
    37. Y. S. Chauhan,"Modeling of futuristic FinFETand Nanowire transistors", IEEE International Conference on Emerging Electronics (ICEE), Mumbai, India, Dec. 2016.
    38. Y. S. Chauhan,"Modeling of high power and high frequency GaN-HEMTs using ASM-HEMT compact model", International Conference of Young Researchers on Advanced Materials (IUMRS-ICYRAM 2016), Bangalore, Dec. 2016.
    39. Y. S. Chauhan, "Negative Capacitance Transistor - Breaking 60mV/decade barrier in conventional CMOS process", IEEE Workshop on Electron Devices, Allahabad, Nov. 2016.
    40. A. Ahsan, S. Ghosh, S. Khandelwal, MA Long and, Y. S. Chauhan, "ASM-HEMT Model for GaN RF and Power Electronic Applications: Overview and Extraction", MOS-AK Workshop, Sanghai, China, June 2016.
    41. Y. S. Chauhan, "Modeling of FinFET and Naowire Transistor using industry standard BSIM-CMG model", International Symposium on the Physics of Semiconductors and Applications, Korea, July 2016.
    42. Y. S. Chauhan, "Compact Modeling of FinFET and Nanowire Transistor", National Conference on Semiconductor Materials and Devices, IIT Jodhpur, March 2016.
    43. Y. S. Chauhan, "Compact MOSFET Modeling", VIT University, Vellore, Tamilnadu, Feb. 2016.
    44. Y. S. Chauhan, "Modeling of FinFET and FDSOI Transistor", College of Engineering, Chengannur, Kerala, Dec. 2015.
    45. Y. S. Chauhan, "ASM-HEMT: Advanced SPICE Model for GaN HEMTs", Space Application Center - Indian Space Research Organization, Ahmedabad, Sept. 2015.
    46. Y. S. Chauhan, "Compact MOSFET Modeling", Semi-Conductor Laboratory, Mohali-Chandigarh, Aug. 2015.
    47. Y. S. Chauhan, "MOSFET to FinFET: Economics and Physics", Thapar University, Patiala, Aug. 2015.
    48. Y. S. Chauhan, "Finfet modeling for 10nm and beyond - Si, Ge and III-V channel", Indo-French Workshop on Emerging Trends in Electron Device Modeling, Bangalore, March 2015.
    49. S. Khandelwal, T. A. Fjeldly, Y. S. Chauhan, B. Iniguez, S. Ghosh, A. Dasgupta, K. Sharma, "ASM-HEMT Model: A Physics-based Compact Model for GaN HEMTs", MOS-AK Workshop, Berkeley, USA, Dec. 2014.
    50. Y. S. Chauhan, J. P. Duarte, H. Agarwal, S. Khandelwal, C. Hu, "Recent Enhancements in BSIM6 and BSIM-CMG models", MOS-AK Workshop, Berkeley, USA, Dec. 2014.
    51. Y. S. Chauhan, "Compact Modeling of Semiconductor Devices - MOSFET", Tutorial in IEEE International Conference on Emerging Electronics, December 2014.
    52. Y. S. Chauhan, "Semiconductor industry - Challenges and Opportunities", Institute of Engineering and Technology, DAVV, Indore, November 2014.
    53. Y. S. Chauhan, "High Performance Transistors: Present & Future trends", SGSITS, Indore, November 2014.
    54. H. Agarwal, Y. S. Chauhan, "Flicker Noise Modeling in BSIM6 Compact Model", MOS-AK Workshop, Venice, Italy, Sept. 2014.
    55. Y. S. Chauhan, "Compact Modeling of FinFET and Ultra-Thin-Body devices", INUP Workshop on Compact Modeling, Bangalore, August 2014.
    56. H. Agarwal, S. Khandelwal, Y. S. Chauhan, and C. Hu, "Noise Modeling in BSIM6 Compact Model", Workshop on Compact Modeling, Washington D.C., USA, June 2014.
    57. C. Yadav, S. Khandelwal, and Y. S. Chauhan, "Modeling of AlGaN/GaN FinFET", Workshop on Compact Modeling, Washington D.C., USA, June 2014.
    58. Y. S. Chauhan, "Semiconductor industry: CMOS technology and beyond", Motilal Nehru National Institute of Technology Allahabad, April 2014.
    59. Y. S. Chauhan, "Industry Standard SPICE Modeling", Solid State Physics Laboratory (SSPL) - DRDO, Delhi, June 2013.
    60. Y. S. Chauhan, M. Chalkiadaki, S. Venugopalan, M. A. Karim, N. Paydavosi, S. Jandhyala, J. P. Duarte, C. Enz, A. Niknejad, C. Hu, "Global Geometrical Scaling in BSIM6", MOS-AK Workshop, San Francisco, Dec. 2012.
    61. Y. S. Chauhan, M. A. Karim, A. Niknejad, C. Hu, "Thermal Network Extraction in Ultra-Thin-Body SOI MOSFETs", MOS-AK Workshop, Bordeaux, France, Sept. 2012.
    62. Y. S. Chauhan, M. A. Karim, S. Venugopalan, A. Sachid, P. Thakur, N. Paydavosi, A. Niknejad, C. Hu, "BSIM Models: From Multi-Gate to the Symmetric BSIM6", International Workshop on Device Modeling for Microsystems, Noida, March 2012.
    63. Y. S. Chauhan, M. A. Karim, S. Venugopalan, A. Sachid, P. Thakur, N. Paydavosi, A. Niknejad, C. Hu, W. wu, K. Dandu, K. Green, T. Krakowsky, G. Coram, S. Cherepko, S. Sirohi, A. Dutta, R. Williams, J. Watts, M.-A. Chalkiadakim A. Mangla, A. Bazigos, W. Grabinski, C. Enz, "Transitioning from BSIM4 to BSIM6", International Workshop on Device Modeling for Microsystems, Noida, March 2012.
    64. Y. S. Chauhan, M. A. Karim, S. Venugopalan, A. Sachid, A. Niknejad, C. Hu, W. wu, K. Dandu, K. Green, G. Coram, S. Cherepko, J. Wang, S. Sirohi, J. Watts, M.-A. Chalkiadakim A. Mangla, A. Bazigos, F. Krummenacher, W. Grabinski, C. Enz, "BSIM6: Symmetric Bulk MOSFET Model", The Nano-Terra Workshop on the next generation MOSFET Compact Models, Lausanne, Switzerland, Dec. 2011.
    65. M. A. Karim, Y. S. Chauhan, S. Venugopalan, A. Niknejad, C. Hu, "BSIM-IMG: Surface Potential based UTBSOI MOSFET Model", The Nano-Terra Workshop on the next generation MOSFET Compact Models, Lausanne, Switzerland, Dec. 2011.
    66. S. Venugopalan, Y. S. Chauhan, M. A. Karim, A. Niknejad, C. Hu, "BSIM-CMG: Advanced FinFET Model", The Nano-Terra Workshop on the next generation MOSFET Compact Models, Lausanne, Switzerland, Dec. 2011.
    67. A. B. Sachid, Y. S. Chauhan and C. Hu, "Exploring Next-Generation FinFET Architectures for SRAM Applications", MOS-AK Workshop, Washington DC, USA, Dec. 2011.
    68. Y. S. Chauhan, M. A. Karim, S. Venugopalan, A. Sachid, A. Niknejad and C. Hu, "BSIM6: Next generation RF MOSFET Model", MOS-AK Workshop, Washington DC, USA, Dec. 2011.
    69. D. Lu, S. Venugopalan, T. Morshed, Y. S. Chauhan, C-H Lin, M. Dunga, A. Niknejad and C. Hu, "A Multi-Gate CMOS Compact Model - BSIMMG", MOS-AK Workshop, San Francisco, USA, Dec. 2010.
    70. Y. S. Chauhan, F. Krummenacher, C. Anghel, R. Gillon, B. Bakeroot, M. Declercq, and A. M. Ionescu, "A Compact Model for Circuit Simulation of High Voltage Lateral and Vertical DMOS Transistors", ROBUSPIC Power Device Workshop, Napoli, Italy, June 2006.
    71. Y. S. Chauhan, F. Krummenacher, C. Anghel, R. Gillon, B. Bakeroot, M. Declercq, and A. M. Ionescu, "The HV-EKV MOSFET Model", Compact Model Council meeting, Boston, USA, May 2006.