Dr. Avinash Lahgere

Assistant Professor

Department of Electrical Engineering

Indian Institute of Technology Kanpur, India

Lab Logo

Contributions outside the Institute

  1. Technical Program Committee Member : 39th International Conference on VLSI Design (VLSID), 2026
  2. Technical Program Committee Member : 37th Asia-Pacific Microwave Conference (APMC), 2025
  3. Technical Program Committee Member : 29th International Symposium on VLSI Design and Test (VDAT), 2025
  4. Student Engagement Committee Member : 7th IEEE ICEE Conference, 2025
  5. Organizer : IEEE EDS Workshop on Devices and Circuits, Goa, 2025 (more than 50 faculties and students from several IITs, NITs, and others attended 4 days event)
  6. Co-Organizer : IEEE EDS Workshop on Devices and Circuits, Srinagar, 2024
  7. Publicity Vice Chair : IEEE 8th EDTM Conference, 2024
  8. Tutorial Session Chair : IEEE 8th EDTM Conference, 2024
  9. Student Research Forum Co-chair : 8th IEEE EDTM Conference 2024
  10. Technical Session Chair : IEEE 8th EDTM Conference, 2024
  11. Technical Session Chair : IEEE 2nd IATMSI Conference, 2024
  12. Technical Program Committee Member : IEEE GUCON, 2022
  13. Organizer : IEEE EDS Mini-Colloquium, 2024
  14. Organizer : IEEE EDS Mini-Colloquium, 2022
  15. Organizer : IEEE EDS Distinguished Lectures, 2022 – present

Reviewer

  1. IEEE Transcation on Electron Devices
  2. IEEE Electron Device Letter
  3. IEEE Journal of the Electron Devices Society
  4. IEEE IEEE Transactions on Device and Materials Reliability
  5. IET Electronics Letter
  6. IET Circuits, Devices & Systems
  7. Elsevier : Superlattices and Microstructures
  8. AIP Advances
  9. 59th IEEE international Midwest Symposium on Circuits and Systems (MWSCAS)
  10. Scientific Reports - Nature
  11. Indian National Academy of Engineering (INAE)

Invited Talks

  1. Challanges, and Oppertunities: Advanced Nodes SRAM Design, IEEE-EDS Workshop on Semiconductors, Mussoorie, 2025.
  2. Advanced GaN Compact Modeling for Efficient RF Power Amplifier Design, Tutorial at 38th International Conference on VLSI Design and 24th International Conference on Embedded System, Bangalore, 2025.
  3. Wide bandgap Semiconductor Devices, FDP at NIT Patna, 2025.
  4. Cold SRAM for High Performance and Energy Efficient Computing, FDP at NIT Raipur, 2025.
  5. Modeling and Simulation of GaN HEMT Devices, IEEE-EDS Workshop on Devices and Circuits, Srinagar, Jammu and Kashmir, 2025.
  6. Unrevealing the Potential of Tunneling to Design Unified Memory, IEEE EDS Summer School, Indian Institute of Technology Jodhpur, 2025.
  7. Advanced Nodes Modeling and SRAM Design, IEEE-EDS Workshop on Devices and Circuits, Srinagar, 2024.
  8. Electrostatic Discharge (ESD): Overview and Research Opportunities, Indian Institute of Technology Jodhpur EDS Students Chapter, 2024.
  9. Design of Low Trigger Voltage ESD Device, IEEE-EDS Workshop on Devices and Circuits, Khajuraho, 2023.
  10. Designing On-Chip ESD Protection for Integrated Circuits, FDP on the recent trends in VLSI design & its research issues in industry compliance, at G. H. Raisoni College of Engineering, Nagpur, 2023.
  11. On-Chip ESD Protection for Neuromorphic Chips, Indian Institute of Technology Patna, 2023.
  12. In-House Compact Model Development for Diode Reverse Recovery, SPIE student chapter-MNIT Jaipur, 2023.
  13. Electrostatic Discharge (ESD): Overview and Opportunities, 5th International Conference on Trends in Computational and Cognitive Engineering, PSIT Kanpur, 2023.
  14. Scaling Challenges and Research Opportunities for Dynamic Random Access Memory, NITTTR Chandigarh, 2022.
  15. Dynamic Random Access Memory: Challenges and Solutions, PDPM IIITDM Jabalpur, 2022.
  16. Design of Main Memory using Steep Sub Threshold Swing CMOS Device, G. H. Raisoni College of Engineering, Nagpur, 2022.