The continuity of Moore’s law drives the technological advancement from mainframe computers to mobile devices that fit in our pockets. Moreover, to enhance computing performance, a transistor with a small feature size is required to perform better at higher speeds. However, the aggressive scaling of CMOS results in increased short channel effects (SCEs), which restricts the scaling of the CMOS in the sub-10 nm regime. Also, the ever-increasing role stress engineering effect due to scaling raises a major concern regarding the local layout effect (LLE). The LLE has a strong impact on the device and circuit performance in advanced technology nodes. Therefore, these challenges need to be investigated in greater detail. In this area, we would like to address the scaling and LLE challenges of the CMOS. Broadly, our research efforts are:

1. Developing novel devices and circuits for more-of-Moore and more-than-Moore applications


2. Investigating emerging device architecture incorporating new materials that will enable aggressive operating voltage scaling for energy efficient computing applications

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CMOS scaling has fueled innovations that led to an era of the internet of things (IoT) and big data. However, the incessant scaling of the MOSFETs has attained its physical limits particularly due to the Boltzmann tyranny of 60mV/decade sub-threshold swing (SS) which is difficult to scale down below 60mV/decade. Thus, the static power consumption in integrated circuits (ICs) is progressively increasing with conventional MOSFET scaling. The probable solution to overcome this CMOS scaling bottleneck is to enable an alternate conduction mechanism i.e. band-to-band-tunneling or impact ionization based on steep sub-threshold swing devices such as Tunnel FETs (TFETs) and impact ionization MOS (IMOS). In this area, we would like to address the limitation of TFET and IMOS devices. Broadly, our research objectives are:

1. Develop a new TFET and IMOS device platform to demonstrate highly scaled and high performance for von-Neumann computing systems


2. Explore circuit level implementation of TFET and IMOS device in ULSI logic using device-circuit cosimulation approach

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In today’s era, DRAM chips are extensively used in electronic devices such as in main memories of mainframes, workstations, and personal computers and recently in working memories of mobile phones and digital electrical home appliances, thanks to high-speed operations, large integration density, and excellent reliability. Furthermore, we have eye-witnessed an exponential growth in the number of DRAM memory cells per chip due to its inherent simple structure. However, the DRAM scaling has reached its bottleneck in particular due to the capacitor which has become harder to scale, as MOSFET geometries scale. In this area, we would like to address the scaling constraints of the DRAM using single transistor DRAM. The single transistor DRAM exploits tunneling and impact ionization conduction mechanism for memory operations. The key research objectives are:

1. Investigation of the proposed TFET and IMOS devices for single transistor DRAM application


2. Cell array level implementation of TFET and IMOS based single transistor DRAM for PPA analysis

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A compact model is a mathematical representation of all the physical phenomena encountered in semiconductor devices as shown by technology for Computer-Aided Design. The compact model helps to anticipate circuit functionality, performance, and even yield prior to wafer processing. It allows circuit sensitivity analysis such as temperature, voltage supply, or process variations. With the continuous miniaturization of technology nodes, several new effects are coming into the actions, which need to be modeled. In this regard, the key research objectives are:

1. Develop a compact model for novel CMOS devices and circuits


2. Develop a compact model for statistical effects

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The growing demand for the millimeter-wave (mmW) band (30-300 GHz) is driven by its shorter wavelengths and wider frequency bands, enabling the development of smaller components with enhanced performance. Monolithic microwave integrated circuits (MMICs) based on GaN technology play a critical role in fulfilling the requirements of the mmW range. Our reserach interest focused on:

1. Develop a compact model for D-model and E-mode Gan HEMT devices.


2. Examination of GaN-based devices for mmW applications, such as high-power amplifiers, and low noise amplifiers

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Electrostatic discharge (ESD) is a serious threat in the semiconductor industry, capable of causing failures and damage in electronic devices due to rapid electrical charge transfer. Voltages during ESD incidents can exceed device limits, resulting in failures like dielectric breakdown and thermal damage etc. Therefore, our reserach interest focused on:

1. Develop a compact model for ESD protection devices.


2. Investigation novel device architectures for ESD design.



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