CMOS and Beyond CMOS

Device Architecture The continuity of Moore’s law drives the technological advancement from mainframe computers to mobile devices that fit in our pockets. Moreover, to enhance computing performance, a transistor with a small feature size is required to perform better at higher speeds. However, the aggressive scaling of CMOS results in increased short channel effects (SCEs), which restricts the scaling of the CMOS in the sub-10 nm regime. Also, the ever-increasing role stress engineering effect due to scaling raises a major concern regarding the local layout effect (LLE). The LLE has a strong impact on the device and circuit performance in advanced technology nodes. Therefore, these challenges need to be investigated in greater detail. In this area, we would like to address the scaling and LLE challenges of the CMOS. Broadly, our research efforts are:
  1. Developing novel devices and circuits for more-of-Moore and more-than-Moore applications

  2. Investigating emerging device architecture incorporating new materials that will enable aggressive operating voltage scaling for energy efficient computing applications

Steep Sub Threshold Slope FET

Single Transistor Dynamic Random Access Memory

Single Transistor Dynamic Random Access Memory In today’s era, DRAM chips are extensively used in electronic devices such as in main memories of mainframes, workstations, and personal computers and recently in working memories of mobile phones and digital electrical home appliances, thanks to high-speed operations, large integration density, and excellent reliability. Furthermore, we have eye-witnessed an exponential growth in the number of DRAM memory cells per chip due to its inherent simple structure. However, the DRAM scaling has reached its bottleneck in particular due to the capacitor which has become harder to scale, as MOSFET geometries scale. In this area, we would like to address the scaling constraints of the DRAM using single transistor DRAM. The single transistor DRAM exploits tunneling and impact ionization conduction mechanism for memory operations. The key research objectives are:
  1. Investigation of the proposed TFET and IMOS devices for single transistor DRAM application

  2. Cell array level implementation of TFET and IMOS based single transistor DRAM for PPA analysis

Compact Modeling

Compact Modeling A compact model is a mathematical representation of all the physical phenomena encountered in semiconductor devices as shown by technology for Computer-Aided Design. The compact model helps to anticipate circuit functionality, performance, and even yield prior to wafer processing. It allows circuit sensitivity analysis such as temperature, voltage supply, or process variations. With the continuous miniaturization of technology nodes, several new effects are coming into the actions, which need to be modeled. In this regard, the key research objectives are:
  1. Develop a compact model for novel CMOS devices and circuits

  2. Develop a compact model for statistical effects

On-Going Project

1. PI : Reliability Characterization and Modeling of CMOS Devices; Agency: IIT Kanpur; Amount: Rs. 25 Lacs; Duration: 2022 - 2024.

2. PI : Evaluation of Radiation Resiliency on Emerging Single Transistor Dynamic Random Access Memory; Agency: Science and Engineering Research Board (SERB); Amount: Rs. 41 Lacs; Duration: 2023 - 2026.

3. PI : Reliability Characterization of CMOS Devices Measurement Lab: IIT Kanpur; Amount: Rs. 1.05 Crore Duration: 2023 - 2024

4. Co-PI : RF Characterization and Compact Modeling of Wide Band-Gap Gallium Nitride (GaN) Devices for the Next Generation Wireless Communication: Science and Engineering Research Board (SERB); Approved

5. Co-PI : Design and Technology Co-optimization of Stacked Nanosheet RF for 6G Applications(Indo-Taiwan Joint Research); Approved