Dr. Avinash Lahgere

Book Chapters

1. C. Sahu, and A. Lahgere, "Doping-free tunnelling transistors–technology and modelling", Advanced Technologies for Next Generation Integrated Circuits, 2020

Patents

1. M. J. Kumar, and A. Lahgere, "Bipolar Impact Ionization MOSFET", India Patent No. 201711032311, 2024.
2. A. Lahgere, P. P. Manik, P. Javorka, A. Icel, and M. Bajaj, "Transistor with Phase Transition Material Region between Channel Region and each Source/Drain Region", U.S. Patent 11,387,364, 2022.

Publications

1. Md M Ahmad, A. K. Kamal, H. Agarwal, and A. Lahgere, "Revisiting Negative Capacitance Effect for 1T-DRAM Application" , IEEE Transactions on Electron Devices, 2026.
2. H. Raza, H. Amrouch, and A. Lahgere, "Soft Error Analysis in NSFET and FSFET: From Device Physics to Circuit and Memory Impact" , IEEE Transactions on Electron Devices, 2026.
3. N. Choudhary, A. Daus, A. Lahgere, G. Gupta, and P. Duhan, "Comprehensive TCAD-based geometry study on self-aligned coplanar top gate a-IGZO TFTs" , APL Electronic Devices, 2026.
4. Md S. Hussain, A. Sirohi, A. Lahgere, Y. S. Chauhan and, Md W. Akram, "Efficacy of π-Gate in LDMOS for Improved Safe Operating Area and Figure of Merits" , Semiconductor Science and Technology, 2026.

1. M. H. Ansari, A. Lahgere, S. S. Ahsan, and Y. S. Chauhan, "Physics Based SPICE Model of Slant Field Plate GaN HEMTs" , IEEE Transactions on Electron Devices, 2025.
2. H. Raza, Mahdi Benkhalifa, Koshal Kumar, Shivendra Parihar, Y. S. Chauhan, H. Amrouch, and A. Lahgere, "Evaluation of Radiation Resilience, Performance, and Vmin of Sub-3nm FSFET based SRAM Arrays" , IEEE Transactions on Computers, 2025.
3. H. Raza, S. S. Parihar, Y. S. Chauhan, H. Amrouch, and A. Lahgere, "A Comprehensive Vmin Investigation of 5 nm SRAM from 300 K down 10 K" ,IEEE Journal on Exploratory Solid-State Computational Devices and Circuits, 2025.
4. M. H. Ansari, S. Thakur, N. Bajpai, P. Maity, A. Lahgere, S. A. Ahsan, M. Shah, and Y. S. Chauhan, “Comprehensive Analysis and Investigation of GaN LNA for 3-4 GHz using Different Gate-Drain Spacing" ,Microelectronics Engineering, 2025.
5. D. Prakash, N. Kamal and A. Lahgere, "Comprehensive TCAD-Based Single Event Effect Study of TFET-Based 1T DRAM and Crossbar Memory Array" , IEEE Transactions on Device and Materials Reliability, vol. 25, no. 1, pp. 156-162, March 2025.

1. M. H. Ansari, P. Pal, A. Lahgere, Y. Y. Hsieh, M. L. Chou, and Y. S. Chauhan, "Temperature Scalable SPICE Model for Kink Effect in GaN HEMTs for High-Power Applications" , IEEE ICEE, pp. 1-4, 2025.
2. Md. M. Ahmad, H. Raza, and A. Lahgere, "Investigation of Process-Induced Variations at Device-Circuit Level: Nanowire vs Nanotube FETs" , IEEE ICEE, pp. 1-4, 2025.
3. S. Shahin, H. Raza, Y. S. Chauhan, H. Amrouch, and A. Lahgere, "Radiation Reliability of a-IWO TFT-based Complementary Circuits for M-3D Integration" , IEEE ICEE, pp. 1-4, 2025.
4. M. H. Ansari, S. Thakur, A. Lahgere, and Y. S. Chauhan, "Survivability and Power Handling of a Packaged GaN MMIC for RF Front-End Systems" , IEEE MAPCON, pp. 1-4, 2025.
5. S. Thakur, H. Singh, S. Gundla, N. Poluri, A. Lahgere, Y. S. Chauhan, and S. Kumar, "Dual-Band GaN Power Amplifier Covering Wide Frequency Ratio for Sub-6 GHz 5G Application" , IEEE MAPCON, pp. 1-4, 2025.
6. S. Thakur, H. Singh, S. Sharma, N. Poluri, A. Lahgere, Y. S. Chauhan, and S. Kumar, "Graphical Method for Designing Distributed Matching Network for Broadband GaN PAs" , IEEE MAPCON, pp. 1-4, 2025.
7. A. K. Kamal, N. Kamal, A. Lahgere, and S. Kumar "Energy Efficient Negative Capacitance L-Shaped Tunnel Field Effect Transistor" , IEEE TENCON, pp. 1-5, 2025.

1. K. Aggarwal and A. Lahgere, "High-Performance Dielectric Modulated Epitaxial Tunnel Layer Tunnel FET for Label-Free Detection of Biomolecules" ,IEEE Open Journal of Nanotechnology, vol. 5, pp. 116-123, 2024.
2. G. Gill, A. Singhal, G. Pahwa, A. Lahgere and H. Agarwal, "A Comprehensive Analysis of Safe Operating Area Limits in Ferroelectric-Based DEMOS" ,IEEE Transactions on Electron Devices, vol. 71, no. 12, pp. 7270-7276, Dec. 2024.
3. A. Lahgere, A. K. Kamal, and R. Kumar, "Band-to-Band Tunneling based Unified RAM (URAM) for Low Power Embedded Applications" , IEEE Transactions on Nanotechnology, 2024 (Accepted).

1. G. Samykutha, S. Sharma, N. Poluri, A. Lahgere and S. Kumar, "A Novel Dual-Band Matching Circuit Covering Wide Frequency Ratio suitable for 5G applications" , IEEE Microwaves, Antennas, and Propagation Conference (MAPCON), pp. 1-5, 2024.
2. A. Singhal, G. Gill, A. Lahgere, G. Pahwa, and H. Agarwal, "Improved Compact Modeling of Snapback Behaviour in ESD MOSFETs" , International Conference on Simulation of Semiconductor Processes and Devices (SISPAD), pp. 01-04, 2024.
3. A. K. Kamal, N. Kamal and A. Lahgere, "Scalability Prespective of Nanotube TFET Capacitorless DRAM in Sub-20 nm Regime" , IEEE LAEDC, pp. 01-04, 2024.
4. H. Raza and A. Lahgere, "AC Performance Benchmarking of Forksheet FET using Ring Oscillator and 6T-SRAM Cell", IEEE Electron Devices Technology and Manufacturing (EDTM), 2024 2024 {Accepted for Poster Presentation}.

1. A. Lahgere and D. S. Gupta, "A Simulation Study of Bipolar I-MOS for ESD Protection" , IEEE Transactions on Electron Devices,vol. 70, no. 12, pp. 6687-6690, Dec. 2023, doi: 10.1109/TED.2023.3321013
2. A. Lahgere and D. S. Gupta, "Gate Grounded Trench I-MOS as an ESD Clamp for Sub-2V Applications" , IEEE Access, vol. 11, pp. 108938-108943, 2023, doi: 10.1109/ACCESS.2023.3321858.
3. A. Lahgere, "Design of Leaky Integrate and Fire Neuron for Spiking Neural Networks using Trench Bipolar I-MOS" , IEEE Transactions on Nanotechnology, vol. 22, pp. 260-265, 2023, doi: 10.1109/TNANO.2023.3278537.
4. N. Kamal, J. Singh, A. Lahgere, and P. K. Tiwari, "Ultra-low Power Reconfigurable Synaptic and Neuronal Transistor for Spiking Neural Network" , IEEE Transactions on Nanotechnology, vol. 22, pp. 245-251, 2023, doi: 10.1109/TNANO.2023.3273624.

1. N. Kamal, A. Lahgere and J. Singh, "Evaluation of Radiation Resiliency on Emerging Junctionless/Dopingless Devices and Circuits" , IEEE Transactions on Device and Materials Reliability, vol. 19, no. 4, pp. 728-732, Dec. 2019.

1. A. Lahgere and M. J. Kumar, "1-T Capacitorless DRAM Using Laterally Bandgap Engineered Si-Si:C Heterostructure Bipolar I-MOS for Improved Sensing Margin and Retention Time" , IEEE Transactions on Nanotechnology, vol. 17, no. 3, pp. 543-551, May 2018.

1. A. Lahgere and M. J. Kumar, "A Tunnel Dielectric-Based Junctionless Transistor With Reduced Parasitic BJT Action" , IEEE Transactions on Electron Devices, vol. 64, no. 8, pp. 3470-3475, Aug. 2017.
2. A. Lahgere and M. J. Kumar, ""1-T Capacitorless DRAM Using Bandgap-Engineered Silicon-Germanium Bipolar I-MOS" , IEEE Transactions on Electron Devices, vol. 64, no. 4, pp. 1583-1590, April 2017.
3. A. Lahgere and M. J. Kumar, "The Charge Plasma n-p-n Impact Ionization MOS on FDSOI Technology: Proposal and Analysis" , IEEE Transactions on Electron Devices, vol. 64, no. 1, pp. 3-7, Jan. 2017.

1. A. Lahgere, M. Panchore, and J. Singh, "Dopingless ferroelectric tunnel FET architecture for the improvement of performance of dopingless n-channel tunnel FETs" , Superlattice Microst., vol. 96, pp. 16–25, 2016.

1. A. Lahgere, C. Sahu and J. Singh, "PVT-Aware Design of Dopingless Dynamically Configurable Tunnel FET" , IEEE Transactions on Electron Devices, vol. 62, no. 8, pp. 2404-2409, Aug. 2015.
2. A. Lahgere, C. Sahu and J. Singh, "Electrically doped dynamically configurable field-effect transistor for low-power and high-performance applications" , IET Electron. Lett., vol. 51, no. 16, pp. 1284–1286, Aug. 2015.

1. C. Sahu, A. Lahgere, and J. Singh, "A dynamically configurable silicon nanowire field effect transistor based on electrically doped source/drain ,arXiv preprint arXiv:1412.4975, 2014.