Publications
Journals:
A. Lahgere, A. K. Kamal, and R. Kumar "Band-to-Band Tunneling based Unified RAM (URAM) for Low Power Embedded Applications", IEEE Transactions on Nanotechnology, 2024 (Accepted).
Conferences:
A. Singhal, G. Gill, A. Lahgere, G. Pahwa, and H. Agarwal "Improved Compact Modeling of Snapback Behaviour in ESD MOSFETs", SISPAD 2024 (Accepted).
A. K. Kamal, N. Kamal and A. Lahgere "Scalability Prespective of Nanotube TFET Capacitorless DRAM in Sub-20 nm Regime", IEEE Latin American Electron Devices Conference (LAEDC), May 2024.
H. Raza and A. Lahgere, "AC Performance Benchmarking of Forksheet FET using Ring Oscillator and 6T-SRAM Cell", EDTM 2024 {Accepted for Poster Presentation}
Journals:
A. Lahgere and D. S. Gupta "A Simulation Study of Bipolar I-MOS for ESD Protection", IEEE Transactions on Electron Devices, vol. 70, no. 12, pp. 6687-6690, Dec. 2023, doi: 10.1109/TED.2023.3321013.
A. Lahgere and D. S. Gupta "Gate Grounded Trench I-MOS as an ESD Clamp for Sub-2V Applications", IEEE Access, vol. 11, pp. 108938-108943, 2023, doi: 10.1109/ACCESS.2023.3321858.
A. Lahgere "Design of Leaky Integrate and Fire Neuron for Spiking Neural Networks using Trench Bipolar I-MOS", IEEE Transactions on Nanotechnology, vol. 22, pp. 260-265, 2023, doi: 10.1109/TNANO.2023.3278537.
N. Kamal, J. Singh, A. Lahgere, and P. K. Tiwari, "Ultra-low Power Reconfigurable Synaptic and Neuronal Transistor for Spiking Neural Network", IEEE Transactions on Nanotechnology, vol. 22, pp. 245-251, 2023, doi: 10.1109/TNANO.2023.3273624.
Patents:
A. Lahgere, P. P. Manik, P. Javorka, A. Icel, and M. Bajaj, "Transistor with Phase Transition Material Region between Channel Region and each Source/Drain Region", US Patent App. 17/087,681, 2022.
Book Chapter:
C. Sahu, and A. Lahgere, "Doping-free tunnelling transistors–technology and modelling", Advanced Technologies for Next Generation Integrated Circuits, 2020.
Journal:
N. Kamal, A. Lahgere and J. Singh, "Evaluation of Radiation Resiliency on Emerging Junctionless/Dopingless Devices and Circuits," IEEE Transactions on Device and Materials Reliability, vol. 19, no. 4, pp. 728-732, Dec. 2019.
Journal:
A. Lahgere and M. J. Kumar, "1-T Capacitorless DRAM Using Laterally Bandgap Engineered Si-Si:C Heterostructure Bipolar I-MOS for Improved Sensing Margin and Retention Time," IEEE Transactions on Nanotechnology, vol. 17, no. 3, pp. 543-551, May 2018.
Journal:
A. Lahgere and M. J. Kumar, "A Tunnel Dielectric-Based Junctionless Transistor With Reduced Parasitic BJT Action," IEEE Transactions on Electron Devices, vol. 64, no. 8, pp. 3470-3475, Aug. 2017.
A. Lahgere and M. J. Kumar, "1-T Capacitorless DRAM Using Bandgap-Engineered Silicon-Germanium Bipolar I-MOS," IEEE Transactions on Electron Devices, vol. 64, no. 4, pp. 1583-1590, April 2017.
A. Lahgere and M. J. Kumar, "The Charge Plasma n-p-n Impact Ionization MOS on FDSOI Technology: Proposal and Analysis," IEEE Transactions on Electron Devices, vol. 64, no. 1, pp. 3-7, Jan. 2017.
Journal:
A. Lahgere, M. Panchore, and J. Singh, "Dopingless ferroelectric tunnel FET architecture for the improvement of performance of dopingless n-channel tunnel FETs," Superlattice Microst., vol. 96, pp. 16–25, 2016.
Journal:
A. Lahgere, C. Sahu and J. Singh, "PVT-Aware Design of Dopingless Dynamically Configurable Tunnel FET," IEEE Transactions on Electron Devices, vol. 62, no. 8, pp. 2404-2409, Aug. 2015.
A. Lahgere, C. Sahu, and J. Singh, "Electrically doped dynamically configurable field-effect transistor for low-power and high-performance applications," IET Electron. Lett., vol. 51, no. 16, pp. 1284–1286, Aug. 2015.
arXiv:
C. Sahu, A. Lahgere, and J. Singh, "A dynamically configurable silicon nanowire field effect transistor based on electrically doped source/drain," arXiv preprint arXiv:1412.4975, 2014.
