Avinash Lahgere

Dr. Lahgere's Photo

Assistant Professor of Electrical Engineering


ESB2 606
Engineering Science Building-2 (ESB2)
Indian Institute of Technology, Kanpur
Kanpur, Uttar Pradesh
India 208016
TelePhone +91-512-679-2302
E-mail alahgere@iitk.ac.in

Research Interests


Semiconductor Devices, Compact Modeling, Emerging CMOS Devices, Emerging Volatile-Nonvolatile Memory, Variation, PPA Benchmarking, Analog/RF, and Neuromorphic computing.

Brief Biography


Avinash Lahgere is an Assistant Professor of Electrical Engineering at the Indian Institute of Technology Kanpur. Avinash received his master's in Electronics and Communication from the PDPM Indian Institute of Information Technology, Jabalpur, in 2015 and his Ph.D. in Electrical Engineering from the Indian Institute of Technology Delhi, in 2018. He is exploring CMOS and beyond CMOS devices for future logic, memory, and analog/RF applications.

Avinash has ~ 5 years of industry experience with respect to the device compact model development. Prior to joining IIT Kanpur, he was with GlobalFoundries, as a Member of Technical Staff (MTS). He was a part of the design enablement group, where he was majorly involved in SPICE/RF Device model development for advanced node technologies such as 12 nm, 22FDX, and so on. He was also involved in Statistical Modeling, LVS, PEX, and Standard Cell Design and modeling. During his tenure at GF, he has received many Spotlight and Appreciation awards for his outstanding work. In addition, he was also a part of the technical interview committee for hiring the new compact model engineers.

Experience


1. Assistant Professor                         Indian Institute of Technology Kanpur           (May'22 to Present)

2. Member of Technical Staff             GlobalFoundries                                           (July'21 to Apr'22)

3. Principal Engineer                         GlobalFoundries                                           (Aug'17 to June'21)

Reviewer


1. IEEE Transcation on Electron Devices
2. IEEE Electron Device Letter
3. IEEE Journal of the Electron Devices Society
4. IEEE IEEE Transactions on Device and Materials Reliability
5. IET Electronics Letter
6. IET Circuits, Devices & Systems
7. Elsevier : Superlattices and Microstructures
8. AIP Advances
9. 59th IEEE international Midwest Symposium on Circuits and Systems (MWSCAS)
10. Scientific Reports - Nature
11. Indian National Academy of Engineering (INAE)

Technical Program Committee Member


1. GUCON-2022

Invited Talks


1. Scaling Challenges and Research Opportunities for Dynamic Random Access Memory in Short Term Course on Challanges and Opportunities in VLSI Design, NITTTR Chandigarh, on 27th July 2022.
2. Dynamic Random Access Memory: Challenges and Solutions on IEEE Day Celebration Week, PDPM IIITDM Jabalpur, on 10th October 2022.
3. Design of Main Memory using Steep Sub Threshold Swing CMOS Device expert talk at G. H. Raisoni College of Engineering, Nagpur, India, on 15th October 2022.
4. Design of Low Trigger Voltage ESD Device on IEEE-EDS Workshop on Devices and Circuits, Khajuraho, Madhya Pradesh on 26th January 2023.
5. Designing On-Chip ESD Protection for Integrated Circuits FDP on the recent trends in VLSI design & its research issues in industry compliance, at G. H. Raisoni College of Engineering, Nagpur, India, on 6th March 2023..
6. On-Chip ESD Protection for Neuromorphic Chips on Brain-inspired/Neuromorphic Computing for Responsible AI, at Indian Institute of Technology Patna, Bihar, India, on 25th March 2023.
7. In-House Compact Model Development for Diode Reverse Recovery expert talk at SPIE student chapter-MNIT Jaipur, India, on 15th May 2023.
8. Electrostatic Discharge (ESD): Overview and Opportunities expert talk at 5th International Conference on Trends in Computational and Cognitive Engineering, PSIT Kanpur, India, on 24th November 2023.